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ds07-13707-3e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90520a/520b series mb90522a/523a/522b/523b/f523b/v520a n description the mb90520a/520b series is a general-purpose 16-bit microcontroller designed for process control applications in consumer products that require high-speed real-time processing. the microcontroller instruction set is based on the at architecture of the f 2 mc * family with additional instructions for high-level languages, extended addressing modes, enhanced multiplication and division instructions, and a complete range of bit manipulation instructions. the microcontroller has a 32-bit accumulator for processing long word (32-bit) data. the mb90520a/520b series peripheral resources include an 8/10-bit a/d converter, 8-bit d/a converter, uart (sci) , extended i/o serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit ppg timers 0 and 1, a range of i/o timers (16-bit free-run timers 1 and 2, input capture (icu) 0 and 1, and output compare (ocu) 0 and 1) , an lcd controller/driver, 8 external interrupt inputs, and 8 wakeup interrupts. * : f 2 mc stands for fujitsu flexible microcontroller, a registered trademark of fujitsu limited. n features ?clock ? internal pll clock multiplication circuit ? selectable machine clock (pll clock) : base oscillation divided by two or multiplied by one to four (for a 4 mhz base oscillation, the machine clock range is 4 mhz to 16 mhz) . (continued) n packages 120-pin, plastic, lqfp 120-pin, plastic, qfp (fpt-120p-m05) (fpt-120p-m13)
mb90520a/520b series 2 (continued) ? sub-clock (32.768 khz) operation available minimum instruction execution time : 62.5 ns (for oscillation = 4 mhz, pll clock setting = 4, v cc = 5.0 v) ? 16mb cpu memory space internal 24-bit addressing ? instruction set optimized for controller applications rich data types (bit, byte, word, long-word) extended addressing modes (23 types) enhanced signed multiplication and division instructions and reti instruction enhanced calculation precision using a 32-bit accumulator ? instruction set designed for high-level language ( c ) and multi - tasking system stack pointer enhanced pointer-indirect instructions and barrel shift instructions ? faster execution speed 4-byte instruction queue rom mirror function (48 kbytes of bank ff is mirrored in bank 00) ? program patch function : an address match detection function ( 2 addresses ) ? interrupt function 32 programmable interrupts with 8 levels ? automatic data transmission function independent of cpu operation extended intelligent i/o service function (ei 2 os) : up to 16 channels ? low - power consumption ( stand - by ) modes sleep mode (cpu operating clock stops, peripherals continue to operate.) pseudo-clock mode (only oscillation clock and timebase timer continue to operate.) clock mode (main oscillation clock stops, sub-clock and clock timer continue to operate.) stop mode (main oscillation and sub-clock both stop.) cpu intermittent operation mode hardware stand-by mode (change to stop mpde by operating hardware stand-by pins.) ? process cmos technology ? i / o ports general-purpose i/o ports (cmos input/output) : 53 ports general-purpose i/o ports (inputs with pull-up resistors) : 24 ports general-purpose i/o ports (nch open-drain outputs) : 8 ports ? timers timebase timer, clock timer, watchdog timer : 1 channel each 8/16-bit ppg timers 0 and 1 : 8-bit 2 channels or 16-bit 1 channel 16-bit reload timers 0 and 1 : 2 channels 16-bit i/o timers : 16-bit free-run timers 0 and 1 : 2 channels 16-bit input capture 0 : 2 channels (2 channels per unit) 16-bit output compare 0 and 1 : 8 channels (4 channels per unit) 8/16-bit up/down counter/timers 0 and 1 : 8-bit 2 channels or 16-bit 1 channel clock output function : 1 channel ? communications macro ( communication interface ) extended i/o serial interfaces 0 and 1 : 2 channels uart (full-duplex, double-buffered, sci : can also be used for synchronous serial transfer) : 1 channel
mb90520a/520b series 3 ? external event interrupt control function dtp/external interrupts : 8 channels (can be set to detect rising edges, falling edges, h levels, or l levels) wake-up interrupts : 8 channels (detects l levels only) delayed interrupt generation module : 1 channel (for task switching) ? analog / digital conversion 8/10-bit a/d converter : 8 channels (can be initiated by an external trigger. minimum conversion time = 10.2 m s for a 16 mhz machine clock) 8-bit d/a converter : 2 channels (r-2r type. settling time = 12.5 m s for a 16 mhz machine clock) ? display function lcd controller/driver : 32 segment drivers + 4 common drivers ? other supports serial writing to flash memory. (only on versions with on-board flash memory.) note : the mb90520a and 520b series cannot be used in external bus mode. always set these devices to single- chip mode.
mb90520a/520b series 4 n product lineup (continued) parameter part number mb90522a mb90523a mb90522b mb90523b mb90f523b mb90v520a classification mask rom flash rom evaluation product rom size 64 kbytes 128 kbytes 64 kbytes 128 kbytes 128 kbytes ? ram size 4 kbytes 6 kbytes separate emulator power supply *1 ????? no process cmos operating power supply voltage *2 3.0 v to 5.5 v 2.7 v to 5.5 v 3.0 v to 5.5 v internal regulator circuit not mounted mounted cpu functions number of instructions : 340 instruction sizes : 8-bit, 16-bit instruction length : 1 byte to 7 bytes data sizes : 1-bit, 8-bit, 16-bit minimum instruction execution time : 62.5 ns (for a 16 mhz machine clock) interrupt processing time : 1.5 m s min. (for a 16 mhz machine clock) low power operation (standby modes) sleep mode, clock mode, pseudo-clock mode, stop mode, hardware standby mode, and cpu intermittent operation mode i/o ports general-purpose i/o ports (cmos outputs) : 53 general-purpose i/o ports (inputs with pull-up resistors) : 24 general-purpose i/o ports (nch open drain outputs) : 8 total : 85 timebase timer 18-bit counter interrupt interval : 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (for a 4 mhz base oscillation) watchdog timer reset trigger period for a 4 mhz base oscillation : 3.58, 14.33, 57.23, 458.75 ms for 32.768 sub-clock operation : 0.438, 3.500, 7.000, 14.000 s 16-bit i/o timers 16-bit freerun timer number of channels : 2 generates an interrupt on overflow 16-bit output compare number of channels : 8 pin change timing : free run timer register value equals output compare register value. 16-bit input capture number of channels : 2 saves the value of the freerun timer register when a pin input occurs (rising edge, falling edge, either edge) . 16-bit reload timer number of channels : 2 count clock frequency : 0.125, 0.5, or 2.0 m s for a 16 mhz machine clock can be used to count an external event clock.
mb90520a/520b series 5 (continued) *1 : as for the necessity of a dip switch setting (s2) when using the emulation pod (mb2145-507) . refer to the hardware manual for the emulation pod (mb2145-507) fomr details. *2 : take note of the maximum operating frequency and a/d converter precision restrictions when operating at 3.0 v to 3.6 v. see the electrical characteristics section for details. parameter part number mb90522a mb90523a mb90522b mb90523b mb90f523b mb90v520a clock timer 15-bit timer interrupt interval : 0.438, 0.5, or 2.0 m s for sub-clock frequency = 32.768 khz 8/16-bit ppg timer number of channels : 1 (can be used in 2 8-bit channel mode) can generate a pulse waveform output with specified period and 0 to 100 % duty ratio. 8/16 -bit up/down counter/timers number of channels : 1 (can be used in 2 8-bit channel mode) external event inputs : 6 channels reload/compare function : 8-bit 2 channels clock monitor clock output frequency : machine clock/2 1 to machine clock/2 8 delayed interrupt generation module interrupt generation module for task switching. (used by realos.) dtp/external interrupts input channels : 8 generates interrupts to the cpu on rising edges, falling edges with input h level, or l level. can be used for external event interrupts and to activate ei 2 os. wakeup interrupts input channels : 8 triggered by l level. 8/10-bit a/d converter (successive approximation type) number of channels : 8 resolution : 8-bit or 10-bit selectable conversion can be performed sequentially for multiple consecutive channels. single-shot conversion mode : converts specified channel once only. continuous conversion mode : repeatedly converts specified channel. intermittent conversion mode : converts specified channel then halts temporarily. 8-bit d/a converter (r-2r type) number of channels : 2 resolution : 8-bit uart (sci) number of channels : 1 clock synchronous transfer : 62.5 kbps to 1 mbps clock asynchronous transfer : 1202 bps to 31250 bps supports bi-directional and master-slave communications. extended i/o serial interface number of channels : 2 clock synchronous transfer : 31.25 kbps to 1 mbps (using internal shift clock) transmission format : selectable lsb-first or msb-first lcd controller/driver number of common outputs : 4 number of segment outputs : 32 number of power supply pins for lcd drive : 4 lcd display memory : 16 bytes divider resistor for lcd drive : internal
mb90520a/520b series 6 n packages and corresponding products : available, : not available note : see the n package dimensions section for more details. package mb90522a mb90523a mb90522b mb90523b mb90f523b mb90v520a fpt-120p-m05 (lqfp) fpt-120p-m13 (qfp) pga-256c-a01 (pga)
mb90520a/520b series 7 n pin assignment (top view) (fpt-120p-m05) (fpt-120p-m13) rst md0 md1 md2 hst v3 v2 v1 v0 p97 / seg31 p96 / seg30 p95 / seg29 p94 / seg28 p93 / seg27 p92 / seg26 p91 / seg25 x0a x1a p90 / seg24 p87 / seg23 p86 / seg22 p85 / seg21 p84 / seg20 p83 / seg19 p82 / seg18 p81 / seg17 p80 / seg16 v ss p77 / com3 p76 / com2 p31 / ckot p32 / out0 p33 / out1 p34 / out2 p35 / out3 p36 / pg00 p37 / pg01 v cc p40 / pg10 p41 / pg11 p42 / sin0 p43 / sot0 p44 / sck0 p45 / sin1 p46 / sot1 p47 / sck1 seg0 seg1 seg2 seg3 seg4 seg5 seg6 seg7 pa0 / seg8 pa1 / seg9 pa2 / seg10 pa3 / seg11 pa4 / seg12 pa5 / seg13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p30 v ss p27 / adtg p26 / zin0 / int7 p25 / bin0 p24 / ain0 p23 / ic11 p22 / ic10 p21 / ic01 p20 / ic00 p17 / wi7 p16 / wi6 p15 / wi5 p14 / wi4 p13 / wi3 p12 / wi2 p11 / wi1 p10 / wi0 p07 p06 / int6 p05 / int5 p04 / int4 p03 / int3 p02 / int2 p01 / int1 p00 / int0 v cc x1 x0 v ss pa6 / seg14 pa7 / seg15 v ss c p50 / sin2 / ain1 p51 / sot2 / bin1 p52 / sck2 / zin1 dv cc dv ss p53 / da0 p54 / da1 av cc avrh avrl av ss p60 / an0 p61 / an1 p62 / an2 p63 / an3 p64 / an4 p65 / an5 p66 / an6 p67 / an7 v cc p70 / ti0 / out4 p71 / to0 / out5 p72 / ti1 / out6 p73 / to1 / out7 p74 / com0 p75 / com1
mb90520a/520b series 8 n pin descriptions *1 : fpt-120p-m05 *2 : fpt-120p-m13 (continued) pin no. pin name circuit type function lqfp-120 *1 qfp-120 *2 92, 93 x0, x1 a oscillator pin 74, 73 x0a, x1a b sub-oscillator pin 89 to 87 md0 to md2 c input pins for setting the operation mode. connect directly to v cc or v ss . 90 rst c external reset input pin 86 hst c hardware standby input pin 95 to 101 p00 to p06 d general-purpose i/o ports the settings in the pull-up resistor setup register (rdr0) are enabled when ports are set as inputs. the rdr0 settings are ignored when ports are set as outputs. int0 to int6 event input pins for ch.0 to ch.6 of the dtp/external interrupt circuit 102 p07 d general-purpose i/o port the settings in the pull-up resistor setup register (rdr0) are enabled when ports are set as inputs. the rdr0 settings are ignored when ports are set as outputs. 103 to 110 p10 to p17 d general-purpose i/o ports the settings in the pull-up resistor setup register (rdr1) are enabled when ports are set as inputs. the rdr1 settings are ignored when ports are set as outputs. wi0 to wi7 event input pins for the wakeup interrupts. 111, 112, 113, 114 p20, p21, p22, p23 e general-purpose i/o ports ic00, ic01, ic10, ic11 trigger input pins for input capture units (icu) 0 and 1. input operates continuously when channels 0 and 1 of input capture units (icu) 0 and 1 are operating. accordingly, output to the pins from other func- tions that share this pin must be suspended unless performed intentionally. 115 p24 e general-purpose i/o port ain0 also can be used as the count clock a input to 8/16-bit up/down counter/ timer 0. 116 p25 e general-purpose i/o port bin0 also can be used as the count clock b input to 8/16-bit up/down counter/ timer 0. 117 p26 e general-purpose i/o port zin0 also can be used as the control clock z input to 8/16-bit up/down counter/ timer 0. int7 event input pin for ch.7 of the dtp/external interrupt circuit
mb90520a/520b series 9 *1 : fpt-120p-m05 *2 : fpt-120p-m13 (continued) pin no. pin name circuit type function lqfp-120 *1 qfp-120 *2 118 p27 e general-purpose i/o port adtg external trigger input to the 8/10-bit a/d converter input operates continuously when the 8/10-bit a/d converter is performing input. accordingly, output to the pin from other functions that share this pin must be suspended unless performed intentionally. 120 p30 e general-purpose i/o port 1 p31 e general-purpose i/o port ckot output pin for clock monitor function the clock monitor is output when clock monitor output is enabled. 2 p32 e general-purpose i/o port only available when waveform output from output compare 0 is disabled. out0 event output pin for ch.0 of output compare unit 0 (ocu) only available when event output is enabled for output compare unit 0. 3 p33 e general-purpose i/o port only available when waveform output from output compare 1 is disabled. out1 event output pin for ch.1 of output compare unit 0 (ocu) only available when event output is enabled for output compare unit 0. 4 p34 e general-purpose i/o port only available when waveform output from output compare 2 is disabled. out2 event output pin for ch.2 of output compare unit 0 (ocu) only available when event output is enabled for output compare unit 0. 5 p35 e general-purpose i/o port only available when waveform output from output compare 3 is disabled. out3 event output pin for ch.3 of output compare unit 0 (ocu) only available when event output is enabled for output compare unit 0. 6 p36 e general-purpose i/o port only available when waveform output from pg00 is disabled. pg00 output pin for 8/16-bit ppg timer 0 only available when waveform output is enabled for pg00. 7 p37 e general-purpose i/o port only available when waveform output from pg01 is disabled. pg01 output pin for 8/16-bit ppg timer 0 only available when waveform output is enabled for pg01.
mb90520a/520b series 10 *1 : fpt-120p-m05 *2 : fpt-120p-m13 (continued) pin no. pin name circuit type function lqfp-120 *1 qfp-120 *2 9, 10 p40, p41 d general-purpose i/o ports only available when waveform outputs from pg10 and pg11 are disabled. the settings in the pull-up resistor setup register (rdr4) are enabled when ports are set as inputs. the rdr4 settings are ignored when ports are set as outputs. pg10, pg11 output pins for 8/16-bit ppg timer 1 only available when waveform output is enabled for pg10 and pg11. 11 p42 d general-purpose i/o port the settings in the pull-up resistor setup register (rdr4) are enabled when ports are set as inputs. the rdr4 settings are ignored when ports are set as outputs. sin0 uart (sci) serial data input pin input operates continuously when the uart is performing input. accordingly, output to the pin from other functions that share this pin must be suspended unless performed intentionally. 12 p43 d general-purpose i/o port the settings in the pull-up resistor setup register (rdr4) are enabled when ports are set as inputs. the rdr4 settings are ignored when ports are set as outputs. sot0 uart (sci) serial data output pin only available when serial data output is enabled for the uart (sci) . 13 p44 d general-purpose i/o port the settings in the pull-up resistor setup register (rdr4) are enabled when ports are set as inputs. the rdr4 settings are ignored when ports are set as outputs. sck0 uart (sci) serial clock input/output pin only available when serial clock output is enabled for the uart (sci) . 14 p45 d general-purpose i/o port the settings in the pull-up resistor setup register (rdr4) are enabled when ports set as inputs. the rdr4 settings are ignored when ports set are as outputs. sin1 data input pin for extended i/o serial interface 1 input operates continuously when the performing serial input. accordingly, output to the pin from other functions that share this pin must be suspended unless performed intentionally. 15 p46 d general-purpose i/o port the settings in the pull-up resistor setup register (rdr4) are enabled when ports set as inputs. the rdr4 settings are ignored when ports are set as outputs. sot1 data output pin for extended i/o serial interface 1 only available when serial data output is enabled for sot1.
mb90520a/520b series 11 *1 : fpt-120p-m05 *2 : fpt-120p-m13 (continued) pin no. pin name circuit type function lqfp-120 *1 qfp-120 *2 16 p47 d general-purpose i/o port the settings in the pull-up resistor setup register (rdr4) are enabled when ports are set as inputs. the rdr4 settings are ignored when ports are set as outputs. sck1 serial clock input/output pin for extended i/o serial interface 1 only available when serial clock output is enabled for sck1. 35 p50 e general-purpose i/o port sin2 data input pin for extended i/o serial interface 2 input operates continuously when the performing serial input. accordingly, output to the pin from other functions that share this pin must be suspended unless performed intentionally. ain1 also can be used as the count clock a input to 8/16-bit up/down counter/ timer 1. 36 p51 e general-purpose i/o port sot2 data output pin for extended i/o serial interface 2 only available when serial data output is enabled for sot2. bin1 also can be used as the count clock b input to 8/16-bit up/down counter/ timer 1. 37 p52 e general-purpose i/o port sck2 serial clock input/output pin for extended i/o serial interface 2 only available when serial clock output is enabled for sck2. zin1 also can be used as the control clock z input to 8/16-bit up/down counter/ timer 1. 40, 41 p53, p54 i general-purpose i/o ports da0, da1 analog output pins for ch.0 and ch.1 of the 8-bit d/a converter 46 to 53 p60 to p67 k general-purpose i/o ports port input is enabled when the analog input enable register (ader) is set to the ports. an0 to an7 analog inputs for the 8/10-bit a/d converter analog input is enabled when the analog input enable register (ader) is set. 55, 57 p70, p72 e general-purpose i/o ports ti0, ti1 event input pins for 16-bit reload timers 0 and 1 input operates continuously when 16-bit reload timers 0 and 1 input an external clock. accordingly, output to these pins from other functions that share the pins must be suspended unless performed intentionally. out4, out6 event output pins for ch. 4 and ch. 6 of output compare unit 1 (ocu) only available when event output from output compare 1 is enabled.
mb90520a/520b series 12 *1 : fpt-120p-m05 *2 : fpt-120p-m13 (continued) pin no. pin name circuit type function lqfp-120 *1 qfp-120 *2 56, 58 p71, p73 e general-purpose i/o ports only available when event outputs from 16-bit reload timers 0 and 1 are disabled. to0, to1 output pins for 16-bit reload timers 0 and 1. only available when output is enabled for 16-bit reload timers 0 and 1. out5, out7 event output pins for ch. 5 and ch. 7 of output compare unit 1 (ocu) only available when event output from output compare 1 is enabled. 59 to 62 p74 to p77 l general-purpose i/o ports only available when the lcd controller/driver control register is set to the ports. com0 to com3 common pins for the lcd controller/driver only available when the lcd controller/driver control register is set to the common outputs. 64 to 71 p80 to p87 l general-purpose i/o ports only available when the lcd controller/driver control register is set to the ports. seg16 to seg23 lcd segment output pins for the lcd controller/driver only available when the lcd controller/driver control register is set to the segment outputs. 72, 75 to 81 p90, p91 to p97 m general-purpose i/o ports (support up to i ol = 10 ma) only available when the lcd controller/driver control register is set to the ports. seg24, seg25 to seg31 lcd segment output pins for the lcd controller/driver only available when the lcd controller/driver control register is set to the segment outputs. 17 to 24 seg0 to seg7 f lcd segment 00 to 07 pins for the lcd controller/driver 25 to 32 pa0 to pa7 l general-purpose i/o ports only available when the lcd controller/driver control register is set up to the ports. seg8 to seg15 lcd segment 08 to 15 pins for the lcd controller/driver only available when the lcd controller/driver control register is set to the segment outputs.
mb90520a/520b series 13 (continued) *1 : fpt-120p-m05 *2 : fpt-120p-m13 pin no. pin name circuit type function lqfp-120 *1 qfp-120 *2 34 c g capacitor connection pin for stabilizing power supply connect an external ceramic capacitor of approximately 0.1 m f. if operat- ing at 3.3 v or lower, connect to v cc . 82 to 85 v0 to v3 n power supply input pins for the lcd controller/driver 8, 54, 94 v cc power supply power supply input pins for the digital circuit 33, 63, 91, 119 v ss power supply gnd level power supply input pins for the digital circuit 42 av cc h power supply input for the analog circuit ensure that a voltage greater than av cc is applied to v cc before turning the analog power supply on or off. 43 avrh j h reference voltage for the a/d converter ensure that a voltage greater than avrh is applied to av cc before turning the power supply to this pin on or off. 44 avrl h l reference voltage for the a/d converter 45 av ss h gnd level power supply input pin for the analog circuit 38 dv cc h h reference voltage for the d/a converter ensure that this voltage does not exceed v cc . 39 dv ss h l reference voltage for the d/a converter apply the same voltage level as v ss .
mb90520a/520b series 14 n i/o circuit type (continued) type circuit remarks a ? high-speed oscillation feedback resistor approx. 1 m w b ? low-speed oscillation feedback resistor approx. 10 m w c ? hysteresis input d ? selectable pull-up option ? cmos hysteresis input ? cmos level output ? with standby control e ? cmos hysteresis input ? cmos level output ? with standby control x0 x1 nch nch pch clock input standby control signal pch x0a x1a nch clock input standby control signal nch pch pch r hysteresis input r i ol = 4 ma pch pull-up connect/ disconnect selection signal pch nch v cc digital output digital output hysteresis input standby control v ss i ol = 4 ma digital output digital output hysteresis input standby control v cc v ss r nch pch
mb90520a/520b series 15 (continued) type circuit remarks f ? segment output pins g ? capacitor connection pin (this is an n.c. pin on the mb90522a and mb90523a.) h ? analog power supply input protection circuit i ? cmos hysteresis input ? cmos level output (cmos output is not available when analog output is operating.) ? also used as analog output (analog output has priority) ? with standby control j ? a/d converter ref + power supply input pin (incorporates power supply protection circuit.) r nch v cc v ss pch nch v cc v ss avp pch nch v cc v ss r i ol = 4 ma digital output digital output hysteresis input standby control analog output v cc v ss nch pch ane avp ane v cc v ss pch pch nch nch
mb90520a/520b series 16 (continued) type circuit remarks k ? cmos hysteresis input ? cmos level output ? also used as analog input. ? with standby control l ? cmos hysteresis input ? cmos level output ? also used as segment output pin. ? with standby control (only available when segment output is not operating.) m ? cmos hysteresis input ? n-ch open-drain output ? also used as segment output pin. ? with standby control (only available when segment output is not operaing.) n ? reference voltage pin for lcd controller r pch nch v cc v ss i ol = 4 ma digital output digital output hysteresis input standby control analog input i ol = 4 ma digital output digital output hysteresis input standby control segment output/common output r v cc pch nch v ss i ol = 10 ma open drain hysteresis input standby control segment output r v cc nch pch v ss r i ol = 10 ma nch pch v cc v ss
mb90520a/520b series 17 n handling devices take note of the following points when handling devices : ? do not exceed maximum rated voltage (to prevent latch-up) ? supply voltage stability ? power-on precautions ? power supply pins ? crystal oscillator circuit ? notes on using an external clock ? precautions when not using sub-clock mode ? treatment of unused pins ? treatment of n.c. pins ? treatment of pins when a/d converter is not used ? sequence for connecting and disconnecting the a/d converter power supply and analog input pins ? shared use of general-purpose i/o ports and lcd controller/driver seg/com pins ? conditions when output from ports 0 and 1 is undefined ? initialization ? notes on using the div a, ri and divw a, rwi instructions ? notes on using realos device handling precautions ? do not exceed maximum rated voltage ( to prevent latch - up ) latch-up occurs in cmos ics if a voltage greater than v cc or less than v ss is applied to an input or output pin (other than a high or medium withstand voltage pin) or if the voltage applied between v cc and v ss exceeds the rating. if latch-up occurs, the power supply current increases rapidly resulting in thermal damage to circuit elements. therefore, ensure that maximum ratings are not exceeded in circuit operation. similarly, when turning the analog power supply on or off, ensure the analog power supply voltages (av cc , avrh, dv cc ) and analog input voltages do not exceed the digital voltage (v cc ) . also ensure that the voltages applied to the lcd power supply pins (v3 to v0) do not exceed the power supply voltage (v cc ) . ? supply voltage stability rapid changes in supply voltage may cause the device to misoperate, even if the voltage remains within the allowed operating range. accordingly, ensure that the v cc supply is stable. the standard for power supply voltage stability is a peak-to-peak v cc ripple voltage at the mains supply frequency (50 to 60 hz) of 10 % or less of v cc and a transient voltage change rate of 0.1 v/ms or less when turning the power supply on or off. ? power - on precautions to prevent misoperation of the internal regulator circuit at power-on, ensure that the power supply rising time (0.2 v to 2.7 v) is at least 50 m s. ? power supply pins when multiple v cc and v ss pins are provided, connect all v cc and v ss pins to power supply or ground externally. although pins at the same potential are connected together in the internal device design so as to prevent misoperation such as latch-up, connecting all v cc and v ss pins appropriately minimizes unwanted radiation, prevents misoperation of strobe signals due to increases in the ground level, and keeps the overall output current rating. also, ensure that the impedance of the v cc and v ss connections to the power supply are as low as possible.
mb90520a/520b series 18 connection of a bypass capacitor of approximately 0.1 m f between v cc and v ss is recommended to prevent power supply noise. connect the capacitor close to the v cc and v ss pins. ? crystal oscillator circuit noise on the x0 and x1 pins can be a cause of device misoperation. place the x0 and x1 pins, crystal oscillator (or ceramic oscillator) , and bypass capacitor to ground as close together as possible. also, design the circuit board so that the x0 and x1 pin wiring does not cross other wiring. surrounding the x0/x1 and x0a/x1a pins with ground in the printed circuit board design is recommended to ensure stable operation. ? notes on using an external clock when using an external clock, drive the x0 pin only and leave the x1 pin open. the figure below shows an example of how to use an external clock. ? precautions when not using sub - clock mode connect an oscillator to x0a and x1a, even if not using sub-clock mode. ? treatment of unused pins leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to latchup. always pull-up or pull-down unused pins using a 2 k w or larger resistor. if some i/o pins are unused, either set as outputs and leave open circuit or set as inputs and treat in the same way as input pins. ? treatment of n.c. pins always leave n.c. (non connect) pins open circuit. ? treatment of pins when a / d converter not used when not using the a/d converter and d/a converter, always connect av cc = dv cc = avrh = v cc and av ss = avrl = v ss . ? sequence for connecting and disconnecting the a / d converter power supply and analog input pins do not apply voltage to the a/d and d/a converter power supply (av cc , avrh, avrl, dv cc , dv ss ) or analog inputs (an0 to an7) until the digital power supply (v cc ) is turned on. when turning the device off, turn off the digital power supply after disconnecting the a/d converter power supply and analog inputs. when turning the power on or off, ensure that avrh and dv cc do not exceed av cc (turning the analog and digital power supplies on and off simultaneously is ok) . ? shared use of general - purpose i / o ports and lcd controller / driver seg / com pins the seg08 to seg31 and com0 to com3 pins are shared with general-purpose i/o ports. the electrical ratings for seg08 to seg23 and com0 to com3 are the same as for cmos outputs and the electrical ratings for seg24 to seg31 are the same as for n-ch open-drain ports. x0 open circuit mb90520a/520b series x1 example of how to use an external clock
mb90520a/520b series 19 ? conditions when output from ports 0 and 1 is undefined after turning on the power supply, the outputs from ports 0 and 1 are undefined during the oscillation stabili- zation delay time controlled by the regulator circuit (during the power-on reset) . the figure below shows the timing. note that this undefined output period does not occur on products without an internal regulator circuit as these products do not have an oscillation stabilization delay time. note : see the n product lineup section for details of which mb90520a/520b series products have an internal regulator circuit. ? initialization the device contains internal registers that are only initialized by a power-on reset. to initialize these registers, restart the power supply. ? notes on using the div a , ri and divw a , rwi instructions set the corresponding bank registers (dtb, adb, usb, ssb) to 00 h when using the signed division instruc- tions div a, ri and divw a, rwi. if the corresponding bank registers (dtb, adb, usb, ssb) are set to other than 00 h , the remainder value produced by the instruction is not stored in the instruction operand register. ? notes on using realos the extended intelligent i/o service (ei 2 os) cannot be used when using realos. caution on operations during pll clock mode if the pll clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. performance of this operation, however, cannot be guaranteed. v cc (power supply pin) ponr (power-on reset) signal rst (external asynchronous reset) signal rst (internal reset) signal oscillation clock signal ka (internal operating clock a) signal kb (internal operating clock b) signal port (port output) signal oscillation stabilization delay time *2 undefined output time regulator circuit stabilization delay time *1 *1 : regulator circuit oscillation stabilization delay time : 2 17 /oscillation clock frequency (approx. 8.19 ms for a 16 mhz oscillation clock frequency) *2 : oscillation stabilization delay time : 2 18 /oscillation clock frequency (approx. 16.38 ms for a 16 mhz oscillation clock frequency) timing chart for undefined output from ports 0 and 1
mb90520a/520b series 20 ? block diagram f 2 mc-16lx cpu x0, x1 x0a, x1a rst hst p00/int0 to p06/int6 p10/wi0 to p17/wi7 p60/an0 to p67/an7 seg00 to seg07 v0 to v3 p74/com0 to p77/com3 p70/ti0/out4 p71/to0/out5 p72/ti1/out6 p73/to1/out7 p20/ic00 p21/ic01 p22/ic10 p23/ic11 p24/ain0 p25/bin0 p26/zin0/int7 p32/out0 p33/out1 p34/out2 p35/out3 p42/sin0 p43/sot0 p44/sck0 p31/ckot p30 p37/pg01 p36/pg00 p41/pg11 p40/pg10 7 7 3 8 4 4 p80/seg16 to p87/seg23 8 24 p90/seg24 to p97/seg31 8 pa0/seg08 to pa7/seg15 8 4 av cc av ss dv cc dv ss avrh avrl p07 p45/sin1 p46/sot1 p47/sck1 p27/adtg p50/sin2/ain1 p51/sot2/bin1 p52/sck2/zin1 p53/da0 p54/da1 2 4 2 2 8 8 88 sio ch.1 uart (sci) wakeup interrupts sio ch.2 8-bit d/a converter 2 ch ram rom 4 2 main clock dtp/ external interrupt circuit lcd controller/ driver 8/16-bit up/down counter/ timer 0, 1 port 0 *2 ports 8, 9 *3 , a port 4 *2 port 1 *2 port 2 port 7 port 6 port 2 port 5 interrupt controller 8/10-bit a/d converter port 3 clock controller *1 (includes timebase timer) sub-clock 16-bit i/o timer 1 input capture 0 (icu) 16-bit reload timer 0 output compare 1 (ocu) 16-bit freerun timer 1 16-bit reload timer 1 16-bit i/o timer 2 16-bit freerun timer 0 output compare 0 (ocu) 8/16-bit ppg timer 0, 1 clock output other pins md0 to md2, c, v cc , v ss internal data bus *1 : the clock control circuit includes the watchdog timer and timebase timer low power consumption control circuits. *2 : incorporates a pull-up register setting register. cmos level input and output. *3 : as this port shares pins with the lcd output, the port uses n-ch open-drain circuits.
mb90520a/520b series 21 n memory map note : the upper part of 00 bank contains a mirror of the rom data in ff bank. this is called the mirror rom function and enables use of the c compilers small memory model. as the lower 16 bits of the ff bank and 00 bank addresses are the same, tables located in rom can be referenced without needing to declare far pointers. for example, accessing 00c000 h actually accesses the contents of rom at ffc000 h . note that, as the ff bank rom area exceeds 48 kbytes, the entire rom image cannot be mirrored in 00 bank. accordingly, as rom data from ff4000 h to ffffff h is mirrored in 004000 h to 00ffff h , always locate rom data tables in the range ff4000 h to ffffff h . ffffff h address #1 address #2 address #3 fe0000 h 010000 h 004000 h 002000 h 000100 h 0000c0 h 000000 h single chip mode with mirror function rom area rom area (image of ff bank) ram peripherals registers : internal memory access * : the values of addresses #1, #2, and #3 vary by product. : access prohibited part no. address #1 * address #2 * address #3 * mb90522a/b ff0000 h 004000 h 001100 h mb90523a/b fe0000 h 004000 h 001100 h mb90f523b fe0000 h 004000 h 001100 h mb90v520a ?? 001900 h
mb90520a/520b series 22 n i/o map (continued) address abbreviated register name register name peripheral name initial value 000000 h pdr0 port 0 data register port 0 xxxxxxxx b 000001 h pdr1 port 1 data register port 1 xxxxxxxx b 000002 h pdr2 port 2 data register port 2 xxxxxxxx b 000003 h pdr3 port 3 data register port 3 xxxxxxxx b 000004 h pdr4 port 4 data register port 4 xxxxxxxx b 000005 h pdr5 port 5 data register port 5 xxxxxxxx b 000006 h pdr6 port 6 data register port 6 xxxxxxxx b 000007 h pdr7 port 7 data register port 7 xxxxxxxx b 000008 h pdr8 port 8 data register port 8 xxxxxxxx b 000009 h pdr9 port 9 data register port 9 xxxxxxxx b 00000a h pdra port a data register port a xxxxxxxx b 00000b h lcdcmr port 7/com pin selection register port 7, lcd controller/driver xxxx 0 0 0 0 b 00000c h ocp4 ocu compare register ch.4 16-bit i/o timer xxxxxxxx b 00000d h xxxxxxxx b 00000e h (access prohibited) 00000f h eifr wakeup interrupt flag register wakeup interrupts xxxxxxx0 b 000010 h ddr0 port 0 direction register port 0 0 0 0 0 0 0 0 0 b 000011 h ddr1 port 1 direction register port 1 0 0 0 0 0 0 0 0 b 000012 h ddr2 port 2 direction register port 2 0 0 0 0 0 0 0 0 b 000013 h ddr3 port 3 direction register port 3 0 0 0 0 0 0 0 0 b 000014 h ddr4 port 4 direction register port 4 0 0 0 0 0 0 0 0 b 000015 h ddr5 port 5 direction register port 5 xxx 0 0 0 0 0 b 000016 h ddr6 port 6 direction register port 6 0 0 0 0 0 0 0 0 b 000017 h ddr7 port 7 direction register port 7 0 0 0 0 0 0 0 0 b 000018 h ddr8 port 8 direction register port 8 0 0 0 0 0 0 0 0 b 000019 h ddr9 port 9 direction register port 9 0 0 0 0 0 0 0 0 b 00001a h ddra port a direction register port a 0 0 0 0 0 0 0 0 b 00001b h ader analog input enable register port 6, a/d converter 1 1 1 1 1 1 1 1 b 00001c h ocp5 ocu compare register ch.5 16-bit i/o timer xxxxxxxx b 00001d h xxxxxxxx b 00001e h (access prohibited) 00001f h eicr wakeup interrupt enable register wakeup interrupts 0 0 0 0 0 0 0 0 b
mb90520a/520b series 23 (continued) address abbreviated register name register name peripheral name initial value 000020 h smr serial mode register uart (sci) 0 0 0 0 0 0 0 0 b 000021 h scr serial control register 0 0 0 0 0 1 0 0 b 000022 h sidr/ sodr serial input data register/ serial output data register xxxxxxxx b 000023 h ssr serial status register 0 0 0 0 1 x 0 0 b 000024 h smcs1 serial mode control status register 1 extended i/o serial interface 1 xxxx 0 0 0 0 b 000025 h 0 0 0 0 0 0 1 0 b 000026 h sdr1 serial data register 1 xxxxxxxx b 000027 h cdcr communication prescaler control register communication prescaler register 0 xxx 1 1 1 1 b 000028 h smcs2 serial mode control status register 2 extended i/o serial interface 2 xxxx 0 0 0 0 b 000029 h 0 0 0 0 0 0 1 0 b 00002a h sdr2 serial data register 2 xxxxxxxx b 00002b h (access prohibited) 00002c h ocs45 ocu control status register ch.45 16-bit i/o timer 0 0 0 0 xx 0 0 b 00002d h xxx 0 0 0 0 0 b 00002e h ocs67 ocu control status register ch.67 0 0 0 0 xx 0 0 b 00002f h xxx 0 0 0 0 0 b 000030 h enir dtp/interrupt enable register dtp /external interrupt circuit 0 0 0 0 0 0 0 0 b 000031 h eirr dtp/interrupt request register xxxxxxxx b 000032 h elvr request level setting register 0 0 0 0 0 0 0 0 b 000033 h 0 0 0 0 0 0 0 0 b 000034 h ocp6 ocu compare register ch.6 16-bit i/o timer xxxxxxxx b 000035 h xxxxxxxx b 000036 h adcs a/d control status register 8/10-bit a/d converter 0 0 0 0 0 0 0 0 b 000037 h 0 0 0 0 0 0 0 0 b 000038 h adcr a/d data register xxxxxxxx b 000039 h 0 0 0 0 1 xxx b 00003a h dadr0 d/a converter data register ch.0 8-bit d/a converter xxxxxxxx b 00003b h dadr1 d/a converter data register ch.1 xxxxxxxx b 00003c h dacr0 d/a control register 0 xxxxxxx 0 b 00003d h dacr1 d/a control register 1 xxxxxxx 0 b 00003e h clkr clock output enable register clock monitor function xxxx 0 0 0 0 b
mb90520a/520b series 24 (continued) address abbreviated register name register name peripheral name initial value 00003f h (access prohibited) 000040 h prll0 ppg0 reload register l 8/16-bit ppg timer 0, 1 xxxxxxxx b 000041 h prlh0 ppg0 reload register h xxxxxxxx b 000042 h prll1 ppg1 reload register l xxxxxxxx b 000043 h prlh1 ppg1 reload register h xxxxxxxx b 000044 h ppgc0 ppg0 operation mode control register 0 x 0 0 0 xx 1 b 000045 h ppgc1 ppg1 operation mode control register 0 x 0 0 0 0 0 1 b 000046 h ppgoe ppg0, 1 output control register 0 0 0 0 0 0 0 0 b 000047 h (access prohibited) 000048 h tmcsr0 timer control status register ch.0 16-bit reload timer 0 0 0 0 0 0 0 0 0 b 000049 h xxxx 0 0 0 0 b 00004a h tmr0/ tmrlr0 16-bit timer register ch.0/ 16-bit reload register ch.0 xxxxxxxx b 00004b h xxxxxxxx b 00004c h tmcsr1 timer control status register ch.1 16-bit reload timer 1 0 0 0 0 0 0 0 0 b 00004d h xxxx 0 0 0 0 b 00004e h tmr1/ tmrlr1 16-bit timer register ch.1/ 16-bit reload register ch.1 xxxxxxxx b 00004f h xxxxxxxx b 000050 h ipcp0 icu data register ch.0 16-bit i/o timer xxxxxxxx b 000051 h xxxxxxxx b 000052 h ipcp1 icu data register ch.1 xxxxxxxx b 000053 h xxxxxxxx b 000054 h ics01 icu control status register 0 0 0 0 0 0 0 0 b 000055 h (access prohibited) 000056 h tcdt0 freerun timer data register 0 16-bit i/o timer 0 0 0 0 0 0 0 0 b 000057 h 0 0 0 0 0 0 0 0 b 000058 h tccs0 freerun timer control status register 0 0 0 0 0 0 0 0 0 b 000059 h (access prohibited) 00005a h ocp0 ocu compare register ch.0 16-bit i/o timer xxxxxxxx b 00005b h xxxxxxxx b 00005c h ocp1 ocu compare register ch.1 xxxxxxxx b 00005d h xxxxxxxx b 00005e h ocp2 ocu compare register ch.2 xxxxxxxx b 00005f h xxxxxxxx b
mb90520a/520b series 25 (continued) address abbreviated register name register name peripheral name initial value 000060 h ocp3 ocu compare register ch.3 16-bit i/o timer xxxxxxxx b 000061 h xxxxxxxx b 000062 h ocs01 ocu control status register ch.0, ch.1 0 0 0 0 xx 0 0 b 000063 h xxx 0 0 0 0 0 b 000064 h ocs23 ocu control status register ch.2, ch.3 0 0 0 0 xx 0 0 b 000065 h xxx 0 0 0 0 0 b 000066 h tcdt1 freerun timer data register 1 16-bit i/o timer 0 0 0 0 0 0 0 0 b 000067 h 0 0 0 0 0 0 0 0 b 000068 h tccs1 freerun timer control status register 1 0 0 0 0 0 0 0 0 b 000069 h (access prohibited) 00006a h lcr0 lcdc control register 0 lcd controller/driver 0 0 0 1 0 0 0 0 b 00006b h lcr1 lcdc control register 1 0 0 0 0 0 0 0 0 b 00006c h ocp7 ocu compare register ch.7 16-bit i/o timer xxxxxxxx b 00006d h xxxxxxxx b 00006e h (access prohibited) 00006f h romm rom mirror function selection register rom mirror function selection module xxxxxxx1 b 000070 h to 00007f h vram data memory for lcd display lcd controller/driver xxxxxxxx b 000080 h udcr0 up/down count register 0 8/16-bit up/down counter/timer 0, 1 0 0 0 0 0 0 0 0 b 000081 h udcr1 up/down count register 1 0 0 0 0 0 0 0 0 b 000082 h rcr0 reload compare register 0 0 0 0 0 0 0 0 0 b 000083 h rcr1 reload compare register 1 0 0 0 0 0 0 0 0 b 000084 h csr0 counter status register 0 0 0 0 0 0 0 0 0 b 000085 h (reserved) *3 000086 h ccr0 counter control register 0 8/16-bit up/down counter/timer 0, 1 x 0 0 0 0 0 0 0 b 000087 h 0 0 0 0 0 0 0 0 b 000088 h csr1 counter status register 1 0 0 0 0 0 0 0 0 b 000089 h (reserved) *3 00008a h ccr1 counter control register 1 8/16-bit up/down counter/timer 0, 1 x 0 0 0 0 0 0 0 b 00008b h x 0 0 0 0 0 0 0 b 00008c h rdr0 port 0 input pull-up resistor setup register port 0 0 0 0 0 0 0 0 0 b 00008d h rdr1 port 1 input pull-up resistor setup register port 1 0 0 0 0 0 0 0 0 b
mb90520a/520b series 26 (continued) address abbreviated register name register name peripheral name initial value 00008e h rdr4 port 4 input pull-up resistor setup register port 4 0 0 0 0 0 0 0 0 b 00008f h to 00009d h (access prohibited) (area reserved for system use) *4 00009e h pacsr address detection control register address match detection function 0 0 0 0 0 0 0 0 b 00009f h dirr delayed interrupt request output/clear register delayed interrupt generation module xxxxxxx 0 b 0000a0 h lpmcr low power consumption mode control register low power consumption (standby) mode 0 0 0 1 1 0 0 0 b 0000a1 h ckscr clock selection register 1 1 1 1 1 1 0 0 b 0000a2 h to 0000a7 h (access prohibited) 0000a8 h wdtc watchdog timer control register watchdog timer xxxxxxxx b 0000a9 h tbtc timebase timer control register timebase timer 1 xx 0 0 0 0 0 b 0000aa h wtc clock timer control register clock timer 1 x 0 0 1 0 0 0 b 0000ab h to 0000ad h (access prohibited) 0000ae h fmcs flash memory control status register 1 mbit flash memory 0 0 0 x 0 0 0 0 b 0000af h (access prohibited) 0000b0 h icr00 interrupt control register 00 interrupt controller 0 0 0 0 0 1 1 1 b 0000b1 h icr01 interrupt control register 01 0 0 0 0 0 1 1 1 b 0000b2 h icr02 interrupt control register 02 0 0 0 0 0 1 1 1 b 0000b3 h icr03 interrupt control register 03 0 0 0 0 0 1 1 1 b 0000b4 h icr04 interrupt control register 04 0 0 0 0 0 1 1 1 b 0000b5 h icr05 interrupt control register 05 0 0 0 0 0 1 1 1 b 0000b6 h icr06 interrupt control register 06 0 0 0 0 0 1 1 1 b 0000b7 h icr07 interrupt control register 07 0 0 0 0 0 1 1 1 b 0000b8 h icr08 interrupt control register 08 0 0 0 0 0 1 1 1 b 0000b9 h icr09 interrupt control register 09 0 0 0 0 0 1 1 1 b 0000ba h icr10 interrupt control register 10 0 0 0 0 0 1 1 1 b 0000bb h icr11 interrupt control register 11 0 0 0 0 0 1 1 1 b 0000bc h icr12 interrupt control register 12 0 0 0 0 0 1 1 1 b 0000bd h icr13 interrupt control register 13 0 0 0 0 0 1 1 1 b
mb90520a/520b series 27 (continued) initial value notation *1 : access is prohibited to the address range 0000c0 h to 0000ff h . see the n memory map section. *2 : see the n memory map section for details of the (ram area) . *3 : (reserved areas) are addresses used internally by the system and may not be used. *4 : the (area reserved for system use) contains setting registers used by the evaluation tools. notes : lpmcr, ckscr, and wdtc are initialized by some types of reset and not by others. the initial values listed are for the case when the registers are initialized. the boundary address #### h between the (ram area) and (reserved area) differs depending on the product. see the n memory map section for details. ocu compare registers ch.0 to ch.3 use 16-bit freerun timer 0 and ocu compare registers ch.4 to ch.7 use 16-bit freerun timer 1. note that 16-bit freerun timer 0 is also used by input capture 0 and 1 (icu) . address abbreviated register name register name peripheral name initial value 0000be h icr14 interrupt control register 14 interrupt controller 0 0 0 0 0 1 1 1 b 0000bf h icr15 interrupt control register 15 0 0 0 0 0 1 1 1 b 0000c0 h to 0000ff h (access prohibited) *1 000100 h to 00#### h (ram area) *2 00#### h to 001fef h (reserved area) *3 001ff0 h padr0 detection address setting register 0 (low byte) address match detection function xxxxxxxx b 001ff1 h detection address setting register 0 (middle byte) xxxxxxxx b 001ff2 h detection address setting register 0 (high byte) xxxxxxxx b 001ff3 h padr1 detection address setting register 1 (low byte) xxxxxxxx b 001ff4 h detection address setting register 1 (middle byte) xxxxxxxx b 001ff5 h detection address setting register 1 (high byte) xxxxxxxx b 001ff6 h to 001fff h (reserved area) *3 0 : initial value of bit is 0. 1 : initial value of bit is 1. x : initial value of bit is undefined.
mb90520a/520b series 28 n interrupts, interrupt vectors, and interrupt control registers (continued) interrupt ei 2 os support interrupt vector interrupt control register priority no. address icr address reset #08 ffffdc h ?? high int 9 instruction #09 ffffd8 h ?? exception #10 ffffd4 h ?? 8/10-bit a/d converter #11 ffffd0 h icr00 0000b0 h timebase timer #12 ffffcc h dtp0/dtp1 (external interrupt 0/external interrupt 1) #13 ffffc8 h icr01 0000b1 h 16-bit freerun timer 0 overflow #14 ffffc4 h extended i/o serial interface 1 #15 ffffc0 h icr02 0000b2 h wakeup interrupt #16 ffffbc h extended i/o serial interface 2 #17 ffffb8 h icr03 0000b3 h dtp2/dtp3 (external interrupt 2/external interrupt 3) #18 ffffb4 h 8/16-bit ppg timer 0 counter borrow #19 ffffb0 h icr04 0000b4 h dtp4/dtp5 (external interrupt 4/external interrupt 5) #20 ffffac h 8/16-bit up/down counter/timer 0 compare match #21 ffffa8 h icr05 0000b5 h 8/16-bit up/down counter/timer 0 overflow, up/down direction change #22 ffffa4 h 8/16-bit ppg timer 1 counter borrow #23 ffffa0 h icr06 0000b6 h dtp6/dtp7 (external interrupt 6/external interrupt 7) #24 ffff9c h output compare 1 (ocu) ch.4, ch.5 match #25 ffff98 h icr07 0000b7 h clock timer #26 ffff94 h output compare 1 (ocu) ch.6, ch.7 match #27 ffff90 h icr08 0000b8 h 16-bit freerun timer 1 overflow #28 ffff8c h 8/16-bit up/down counter/timer 1 compare match #29 ffff88 h icr09 0000b9 h 8/16-bit up/down counter/timer 1 overflow, up/down direction change #30 ffff84 h input capture 0 (icu) capture #31 ffff80 h icr10 0000ba h input capture 1 (icu) capture #32 ffff7c h output compare 0 (ocu) ch.0 match #33 ffff78 h icr11 0000bb h output compare 0 (ocu) ch.1 match #34 ffff74 h
mb90520a/520b series 29 (continued) : supported : not supported : supported, includes ei 2 os stop function interrupt ei 2 os support interrupt vector interrupt control register priority no. address icr address output compare 0 (ocu) ch.2 match #35 ffff70 h icr12 0000bc h output compare 0 (ocu) ch.3 match #36 ffff6c h uart (sci) receive complete #37 ffff68 h icr13 0000bd h 16-bit reload timer 0 #38 ffff64 h uart (sci) send complete #39 ffff60 h icr14 0000be h 16-bit reload timer 1 #40 ffff5c h flash memory #41 ffff58 h icr15 0000bf h delayed interrupt generation module #42 ffff54 h low
mb90520a/520b series 30 n peripheral resources 1. i/o ports ? the i/o ports can be used as general-purpose i/o ports (parallel i/o ports) . the mb90520a and 520b series have 11 ports (85 pins) . the ports share pins with the inputs and outputs of the peripheral functions. ? the port data registers (pdr) are used to output data to the i/o pins and capture the input signals from the i/o ports. similarly, the port direction registers (ddr) set the i/o direction (input or output) for each individual port bit. ? the following tables list the i/o ports and peripheral functions with which they share pins. notes ? port 9 contains general-purpose i/o ports with n-ch open-drain output circuits. ? connect an external pull-up resistor when using port 9 pins as outputs. ? port 6 shares pins with the analog inputs. when using port 6 as a general-purpose port, ensure that the corresponding analog input enable register (ader) bits are set to 0. ader is initialized to ff h after a reset. pin name (port) pin name (peripheral) peripheral function that shares pin port 0 p00 - p06 int0 - int6 external interrupts p07 ? not shared port 1 p10 - p17 wi0 - wi7 wakeup interrupts port 2 p20 - p23 in00 - in11 input capture (unit 0) p24, p25 ain0, bin0 8/16-bit up/down counter/timer 0 p26 zin0/int7 8/16-bit up/down counter/timer 0, external interrupt port 3 p30 ? not shared p31 ckot clock monitor function p32 - p35 out0 - out3 output compare (unit 0) p36, p37 ppg00, ppg01 8/16-bit ppg timer 0 port 4 p40, p41 ppg10, ppg11 8/16-bit ppg timer 1 p42 - p44 sin0, sot0, sck0 uart (sci) p45 - p47 sin1, sot1, sck1 extended i/o serial interface 0 port 5 p50 - p52 sin2/ain1, sot1/bin1, sck1/zin1 8/16-bit up/down counter/timer 0 extended i/o serial interface 1 p53, p54 da0, da1 8-bit d/a converter port 6 p60 - p67 an0 - an7 8/16-bit a/d converter port 7 p70 - p73 tin0/out4, tot0/out5, tin1/out6, tot1/out7 16-bit reload timers 0, 1 output compare (unit 1) p74 - p77 com0 - com3 lcd control driver common output port 8 p80 - p87 seg16 - seg23 lcd control driver segment output port 9 p90 - p97 seg24 - seg31 lcd control driver segment output port a pa0 - pa7 seg8 - seg15 lcd control driver segment output
mb90520a/520b series 31 ? block diagrams pch pch nch internal data bus pdr (port data register) pdr read output latch pdr write ddr (port direction register) direction latch ddr write ddr read peripheral function input pull-up resistor option connect/ disconnect setting pin standby control (spl = 1) standby control : controls stop mode (spl = 1) , time-base-timer mode (spl = 1) , clock mode (spl = 1) , and hardware standby mode p00 to p07, p10 to p17 pch nch internal data bus pdr (port data register) pdr read output latch pdr write ddr (port direction register) direction latch ddr write ddr read peripheral function input pin standby control (spl = 1) standby control : controls stop mode (spl = 1) , time-base-timer mode (spl = 1) , clock mode (spl = 1) , and hardware standby mode p20 to p27
mb90520a/520b series 32 pch pch nch internal data bus pdr (port data register) pdr read output latch pdr write ddr (port direction register) direction latch ddr write ddr read peripheral function input* pin standby control (spl = 1) peripheral function output* peripheral function output approval* pull-up resistor option connect/ disconnect setting standby control : controls stop mode (spl = 1) , time-base-timer mode (spl = 1) , clock mode (spl = 1) , and hardware standby mode * : peripheral function i/o is equivalent to i/o of peripheral function. p40 to p47 pch nch internal data bus pdr (port data register) pdr read output latch pdr write ddr (port direction register) direction latch ddr write ddr read peripheral function input* standby control (spl = 1) peripheral function output* peripheral function output approval* pin standby control : controls stop mode (spl = 1) , time-base-timer mode (spl = 1) , clock mode (spl = 1) , and hardware standby mode * : peripheral function i/o is equivalent to i/o of peripheral function. p30 to p37, p50 to p52, p70 to p73
mb90520a/520b series 33 pch nch internal data bus pdr (port data register) pdr read output latch pdr write ddr (port direction register) direction latch ddr write ddr read d/a analog output standby control (spl = 1) d/a analog pin output approval pin standby control : controls stop mode (spl = 1) , time-base-timer mode (spl = 1) , clock mode (spl = 1) , and hardware standby mode p53, p54 pch nch internal data bus pdr (port data register) pdr read output latch pdr write ddr (port direction register) direction latch ddr write ddr read lcd common output standby control (spl = 1) common pin output approval pin standby control : controls stop mode (spl = 1) , time-base-timer mode (spl = 1) , clock mode (spl = 1) , and hardware standby mode p74 to p77
mb90520a/520b series 34 pch nch internal data bus pdr (port data register) pdr read output latch pdr write ddr (port direction register) direction latch ddr write ddr read analog input standby control (spl = 1) pin standby control : controls stop mode (spl = 1) , time-base-timer mode (spl = 1) , clock mode (spl = 1) , and hardware standby mode p60 to p67 pch nch internal data bus pdr (port data register) pdr read output latch pdr write ddr (port direction register) direction latch ddr write ddr read standby control (spl = 1) lcd segment output segment pin output approval pin standby control : controls stop mode (spl = 1) , time-base-timer mode (spl = 1) , clock mode (spl = 1) , and hardware standby mode p80 to p87, pa0 to pa7
mb90520a/520b series 35 nch internal data bus pdr (port data register) pdr read output latch pdr write ddr (port direction register) direction latch ddr write ddr read standby control (spl = 1) lcd segment output segment pin output approval pin standby control : controls stop mode (spl = 1) , time-base-timer mode (spl = 1) , clock mode (spl = 1) , and hardware standby mode p90 to p97
mb90520a/520b series 36 2. timebase timer ? the timebase timer is an 18-bit freerun timer (timebase timer/counter) that counts up synchronized with the main clock (oscillation clock : hclk divided by 2) . ? the timer can generate interrupt requests at a specified interval, with four different interval time settings available. ? the timer supplies the operating clock for peripheral functions including the oscillation stabilization delay timer and watchdog timer. ? timebase timer interval settings ? hclk : oscillation clock frequency ? the values enclosed in ( ) indicate the times for a clock frequency of 4 mhz. ? period of clocks supplied from timebase timer ? hclk : oscillation clock frequency ? the values enclosed in ( ) indicate the times for a clock frequency of 4 mhz. internal count clock period interval time 2/hclk (0.5 m s) 2 12 /hclk (approx. 1.024 ms) 2 14 /hclk (approx. 4.096 ms) 2 16 /hclk (approx. 16.384 ms) 2 19 /hclk (approx. 131.072 ms) peripheral function clock period oscillation stabilization delay for the main clock 2 10 /hclk (approx. 0.256 ms) 2 13 /hclk (approx. 2.048 ms) 2 15 /hclk (approx. 8.192 ms) 2 17 /hclk (approx. 32.768 ms) watchdog timer 2 12 /hclk (approx. 1.024 ms) 2 14 /hclk (approx. 4.096 ms) 2 16 /hclk (approx. 16.384 ms) 2 19 /hclk (approx. 131.072 ms) ppg timer 2 9 /hclk (approx. 0.128 ms)
mb90520a/520b series 37 ? block diagram the actual interrupt request number for the timebase timer is : interrupt request number : #12 (0c h ) tbie tbof tbr tbc1 tbc0 2 1 2 2 2 3 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 of counter clear circuit interval timer selector of of of to ppg timer to watchdog timer to oscillation stabilization delay time selector in clock controller timebase timer/counter hclk divided by 2 reset *1 clear stop mode, etc. *2 switch clock mode *3 tbof clear tbof set timebase timer control register (tbtc) timebase timer interrupt signal of : overflow hclk : oscillation clock frequency *1 : power-on reset, release of hardware standby mode, watchdog reset *2 : clear stop mode, main clock mode, pll clock mode, and pseudo-clock mode *3 : main ? pll clock, sub ? main clock, sub ? pll clock
mb90520a/520b series 38 3. watchdog timer ? the watchdog timer is a timer/counter used to detect faults such as program runaway. ? the watchdog timer is a 2-bit counter that counts the clock signal from the timebase timer or clock timer. ? once started, the watchdog timer must be cleared before the 2-bit counter overflows. if an overflow occurs, the cpu is reset. ? interval time for the watchdog timer * : the difference between the maximum and minimum watchdog timer interval times is due to the timing when the counter is cleared. * : as the watchdog timer is a 2-bit counter that counts the carry-up signal from the timebase timer or clock timer, clearing the timebase timer (when operating on hclk) or the clock timer (when operating on sclk) lengthens the time until the watchdog timer reset is generated. ? watchdog timer count clock ? events that stop the watchdog timer 1 : stop due to a power-on reset 2 : reset due to recovery from hardware standby mode 3 : watchdog reset ? events that clear the watchdog timer 1 : external reset input from the rst pin. 2 : writing 0 to the software reset bit. 3 : writing 0 to the watchdog control bit (second and subsequent times) . 4 : changing to sleep mode (clears the watchdog timer and temporarily halts the count) . 5 : changing to pseudo-clock mode (clears the watchdog timer and temporarily halts the count) . 6 : changing to clock mode (clears the watchdog timer and temporarily halts the count) . 7 : changing to stop mode (clears the watchdog timer and temporarily halts the count) . hclk : oscillation clock (4 mhz) sclk : sub-clock (8.192 khz) min max clock period min max clock period approx. 3.58 ms approx. 4.61 ms 2 14 2 11 / hclk approx. 0.438 s approx. 0.563 s 2 12 2 9 / sclk approx. 14.33 ms approx. 18.30 ms 2 16 2 13 / hclk approx. 3.500 s approx. 4.500 s 2 15 2 12 / sclk approx. 57.23 ms approx. 73.73 ms 2 18 2 15 / hclk approx. 7.000 s approx. 9.000 s 2 16 2 13 / sclk approx. 458.75 ms approx. 589.82 ms 2 21 2 18 / hclk approx. 14.00 s approx. 18.00 s 2 17 2 14 / sclk wtc : wdcs hclk : oscillation clock pclk : pll clock sclk : sub-clock 0 count the clock timer output. count the clock timer output. 1 count the timebase timer output.
mb90520a/520b series 39 ? block diagram ponr stbr wrst erst srst wte wt1 wt0 2 1 2 2 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 2 18 2 4 2 1 2 2 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 4 watchdog timer control register (wdtc) watchdog timer reset change to sleep mode change to pseudo-clock mode change to clock mode change to stop mode counter clear control circuit counter clock selector watchdog timer reset generation circuit 2-bit counter start to internal reset circuit clear main clock (hclk divided by 2) sub-clock (timebase timer/counter) (clock counter) hclk : oscillation clock frequency
mb90520a/520b series 40 4. 8/16-bit ppg (programmable pulse generator) timers 0 and 1 the 8/16-bit ppg timer is a two-channel reload timer module (ppg0 and ppg1) that can generate pulse outputs with the periods specified in the table below and with duty ratios between 0 and 100 % . note that the pulse periods are different depending on the operation mode. *1 : 8 + 8-bit ppg output operation mode consists of using the lower 8 bits as a prescaler for the ppg timer. *2 : the values enclosed in ( ) indicate the times for a machine clock frequency of 16 mhz. operation mode count clock *2 ppg00, ppg01 (ppg ch0) ppg10, ppg11 (ppg ch1) interval time output pulse width interval time output pulse width 8-bit ppg output independent 2ch operation mode f /1 (62.5 ns) 1/ f to 2 8 / f 1/ f to 2 9 / f 1/ f to 2 8 / f 1/ f to 2 9 / f f /2 (125 ns) 2/ f to 2 9 / f 2 2 / f to 2 10 / f 2/ f to 2 9 / f 2 2 / f to 2 10 / f f /4 (250 ns) 2 2 / f to 2 10 / f 2 3 / f to 2 11 / f 2 2 / f to 2 10 / f 2 3 / f to 2 11 / f f /8 (500 ns) 2 3 / f to 2 11 / f 2 4 / f to 2 12 / f 2 3 / f to 2 11 / f 2 4 / f to 2 12 / f f /16 (1000 ns) 2 4 / f to 2 12 / f 2 5 / f to 2 13 / f 2 4 / f to 2 12 / f 2 5 / f to 2 13 / f hclk/512 (128 m s) 2 9 /hclk to 2 17 /hclk 2 10 /hclk to 2 18 /hclk 2 9 /hclk to 2 17 /hclk 2 10 /hclk to 2 18 /hclk 16-bit ppg output operation mode f /1 (62.5 ns) 1/ f to 2 16 / f 1/ f to 2 17 / f 1/ f to 2 16 / f 1/ f to 2 17 / f f /2 (125 ns) 2/ f to 2 17 / f 2 2 / f to 2 18 / f 2/ f to 2 17 / f 2 2 / f to 2 18 / f f /4 (250 ns) 2 2 / f to 2 18 / f 2 3 / f to 2 19 / f 2 2 / f to 2 18 / f 2 3 / f to 2 19 / f f /8 (500 ns) 2 3 / f to 2 19 / f 2 4 / f to 2 20 / f 2 3 / f to 2 19 / f 2 4 / f to 2 20 / f f /16 (1000 ns) 2 4 / f to 2 20 / f 2 5 / f to 2 21 / f 2 4 / f to 2 20 / f 2 5 / f to 2 21 / f hclk/512 (128 m s) 2 9 /hclk to 2 25 /hclk 2 10 /hclk to 2 26 /hclk 2 9 /hclk to 2 25 /hclk 2 10 /hclk to 2 26 /hclk 8 + 8-bit ppg output operation mode *1 f /1 (62.5 ns) 1/ f to 2 6 / f 1/ f to 2 9 / f 1/ f to 2 16 / f 1/ f to 2 17 / f f /2 (125 ns) 2/ f to 2 9 / f 2 2 / f to 2 10 / f 2/ f to 2 17 / f 2 2 / f to 2 18 / f f /4 (250 ns) 2 2 / f to 2 10 / f 2 3 / f to 2 11 / f 2 2 / f to 2 18 / f 2 3 / f to 2 19 / f f /8 (500 ns) 2 3 / f to 2 11 / f 2 4 / f to 2 12 / f 2 3 / f to 2 19 / f 2 4 / f to 2 20 / f f /16 (1000 ns) 2 4 / f to 2 12 / f 2 5 / f to 2 13 / f 2 4 / f to 2 20 / f 2 5 / f to 2 21 / f hclk/512 (128 m s) 2 9 /hclk to 2 17 /hclk 2 10 /hclk to 2 18 /hclk 2 9 /hclk to 2 25 /hclk 2 10 /hclk to 2 26 /hclk
mb90520a/520b series 41 ? ppg timer channels and ppg pins the figure below shows the relationship between the 8/16-bit ppg channels and ppg pins on the mb90520a/ 520b series. ppg0 ppg1 pin pin pin pin ppg00 output pin ppg01 output pin ppg10 output pin ppg11 output pin
mb90520a/520b series 42 ? block diagram ppg00 pin pin clk r sq pen0 pe00 pie0 puf0 reserved ?? ? pcs2 pcs0 pcm2 pcm1 pcm0 pe11 pe01 pcs1 ppg01 3 2 ppg0 reload register prlh0 ("h" level register) ppg0 temporary buffer (prlbh0) reload register "l" level/"h" level selector ppg0 down counter (pcnt0) prll0 ("l" level register) select signal reload underflow clear count start value timebase timer output (hclk/512) peripheral clock ( f /1) peripheral clock ( f /2) peripheral clock ( f /4) peripheral clock ( f /8) peripheral clock ( f /16) "h" level data bus "l" level data bus ppg0 operation mode control register (ppgc0) interrupt request output operation mode control signal ppg1 underflow ppg0 underflow (to ppg1) pulse selector ppg0 output latch invert ppg output control circuit count clock selector select signal ppg01 output control register (ppgoe) ? : undefined reserved : reserved bit hclk : oscillation clock frequency f : machine clock frequency 8/16-bit ppg timer 0
mb90520a/520b series 43 ppg10 ppg11 clk md0 r sq pen1 pe10 pie1 puf1 md1 md0 reserved ? pcs2 pcs0 pcm2 pcm1 pcm0 pe11 pe01 pcs1 3 2 pin pin ppg1 reload register prlh1 ("h" level register) ppg1 temporary buffer (prlbh1) reload selector "l" level/"h" level selector ppg1 down counter (pcnt1) prll1 ("l" level register) select signal reload underflow clear count start value timebase timer output (hclk/512) peripheral clock ( f /1) peripheral clock ( f /2) peripheral clock ( f /4) peripheral clock ( f /8) peripheral clock ( f /16) "h" level data bus "l" level data bus ppg1 operation mode control register (ppgc1) interrupt request output operation mode control signal ppg1 output latch invert ppg output control circuit count clock selector select signal ppg01 output control register (ppgoe) ppg1 underflow (to ppg0) ppg0 underflow (from ppg0) ? : undefined reserved : reserved bit hclk : oscillation clock frequency f : machine clock frequency 8/16-bit ppg timer 1
mb90520a/520b series 44 5. 16-bit reload timers 0 and 1 (with event count function) the 16-bit reload timers have the following functions. ? the count clock can be selected from three internal clock and the external event clock. ? either software trigger or external trigger can be selected as the start signals for 16-bit reload timers 0 and 1. ? an interrupt to the cpu can be generated when an underflow occurs on 16-bit reload timer 0 and 1. this interrupt allows the timers to be used as interval timers. ? two different operation modes can be selected when an underflow occurs on 16-bit reload timer 0 and 1 : one- shot mode in which timer operation halts when an underflow occurs or reload mode in which the reload register value is loaded into the timer and counting continues. ? extended intelligent i/o service (ei 2 os) is supported. ? the mb90520a/520b series contains two 16-bit reload timer channels. ? 16 - bit reload timer operation modes ? interval times for the 16 - bit reload timers note : the values enclosed in ( ) and the example interval times are for a machine clock frequency of 16 mhz. t is the machine cycle and is 1/ (machine clock frequency) . count clock start trigger operation when an underflow occurs internal clock (3 clocks available) software trigger one-shot mode reload mode external trigger one-shot mode reload mode event clock software trigger one-shot mode reload mode external trigger one-shot mode reload mode count clock count clock period example interval times internal clock 2 1 t (0.125 m s) 0.125 m s to 8.192 ms 2 3 t (0.5 m s) 0.5 m s to 32.768 ms 2 5 t (2.0 m s) 2.0 m s to 131.1 ms event clock 2 3 t or longer 0.5 m s or longer
mb90520a/520b series 45 ? block diagram tmrlr tmr clk tin uf en tot clk 3 3 2 f ???? csl1 csl0 mod2 mod1 mod0 oute outl reld uf inte cnte trg internal data bus 16-bit reload register reload signal reload control circuit 16-bit timer register count clock generation circuit machine clock prescaler gate input clock pulse detection circuit clear trigger internal clock pin input control circuit clock selector external clock select signal function selection timer control status register (tmcsr) wait signal output to internal peripheral functions output control circuit output signal generation circuit pin operation control circuit interrupt request output
mb90520a/520b series 46 6. 16-bit i/o timers the 16-bit i/o timers consist of a two-channel 16-bit freerun timer, two-channel input capture, and eight-channel output compare. the output compare channels can be used to generate eight independent waveform outputs based on the 16-bit freerun timer. the input capture channels can be used to measure input pulse widths and external clock periods. ? structure of i / o timers in the mb90520a / 520b series ? 16-bit freerun timer functions ? the count value for the 16-bit freerun timer sets the base time for the input capture and output compare functions. ? an interrupt can be generated when the 16-bit freerun timer overflows. ? extended intelligent i/o service (ei 2 os) can be generated. ? 16-bit freerun timers 0 and 1 can be cleared to 0000 h when an external reset is input, on setting the timer clear bit (tccs : clr = 1) , and when a compare match occurs on output compare 0 to 4. ? the count clock frequency can be selected from the following four clocks : 4/ f (250 ns) , 16/ f (1.0 m s) , 64/ f (4.0 m s) , 256/ f (16.0 m s) note : f is the machine clock frequency. the values in ( ) are for 16 mhz machine clock. ? input capture functions ? the input capture saves the value of the 16-bit freerun timer and generates an interrupt request when the specified edge is detected on the trigger input from the external trigger input pin (ic00 or ic01/ic10 or ic11) . ? input capture channels 0 and 1 can perform input capture and generate interrupt request independently. ? extended intelligent i/o service (ei 2 os) can be generated. ? detection of rising edges, falling edges, or either edge can be selected as the trigger edge. ? when using input capture 0, either the ic00 or ic01 pin can be used. note, however, that masking one pin only is not possible. ? when using input capture 1, either the ic10 or ic11 pin can be used. note, however, that masking one pin only is not possible. ? output compare functions ? the output compare channels compare the values set in output compare registers 0 to 7 with the 16-bit freerun timers 0 and 1 count values and invert the level of the corresponding output compare pin and clear the 16-bit freerun timer to 0000 h when a match is detected. ? extended intelligent i/o service (ei 2 os) can be generated. ? the initial output levels at the output compare pins can be set after the microcontroller boots. ? the output levels from the eight output compare channels are controlled independently. similarly, interrupt requests are also generated independently by each channel. 16-bit freerun timer output compare input capture 16-bit i/o timer (unit 0) 16-bit freerun timer 0 output compare 0 to 3 (unit 0) input capture 0 and 1 (unit 0) 16-bit i/o timer (unit 1) 16-bit freerun timer 1 output compare 4 to 8 (unit 1) ?
mb90520a/520b series 47 ? block diagram ivf reserved ivfe stop mode clr clk1 clk0 of 2 f stop clk clr timer data registers (tcdt0, tcdt1* ) 16-bit counter prescaler timer control status registers (tccs0,tccs1 *) counter value output to input capture and output compare internal data bus output compare register 0 (output compare register 4* ) match signal freerun timer overflow interrupt request f : machine clock frequency of : overflow * : name for 16-bit freerun timer channel 1 16-bit freerun timer icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00 2 2 in00 in01 in10 in11 edge detection circuit pin pin pin pin input capture control status register (ics01) 16-bit freerun timer 0 input capture register 1 (ipcp0) input capture register 0 (ipcp1) internal data bus input capture interrupt request input capture
mb90520a/520b series 48 ??? cmod ote1 ote0 otd1 otd0 iop1 iop0 ioe1 ioe0 ?? cst1 cst0 ??? cmod ote1 ote0 otd1 otd0 iop1 iop0 ioe1 ioe0 ?? cst1 cst0 2 2 2 2 out3 (out7 * ) out2 (out6*) out1 (out5*) out0 (out4*) ocp3 (ocp7 * ) ocp2 (ocp6 * ) ocp1 (ocp5 * ) ocp0 (ocp4 * ) internal data bus output compare control status registers (osc23, osc67*) timer data registers (tcdt0, tcdt1* ) 16-bit freerun timer 0 (1*) compare control circuit 3 (7*) output compare register 3 (7*) compare control circuit 2 (6*) output compare register 2 (6*) compare control circuit 1 (5*) output compare register 1 (5*) compare control circuit 0 (4*) output compare register 0 (4*) output compare control status registers (osc01, osc45*) output compare interrupt request output control circuit 3 (7*) output control circuit 2 (6*) output control circuit 1 (5*) output control circuit 0 (4*) pin pin pin pin output compare interrupt request * : name for output compare unit 1 output compare
mb90520a/520b series 49 7. 8/16-bit up/down counter/timers 0 and 1 ? the 8/16-bit up/down counter/timers can operate in timer mode, up/down count mode, and phase difference count mode. ? the unit can be used as either a 2-channel 8-bit or 1-channel 16-bit up/down counter/timer. ? 8 / 16 - bit up / down counter / timer functions operation mode count mode count clock (count edge) function of zin pin other functions 8-bit 2-channel mode timer mode 2/ f , 4/ f ( f : machine clock frequency) ? compare function reload function compare/reload function compare/reload prohibit the direction of the previous count can be determined from the up/ down flag. interrupt requests can be generated on the following conditions : 1 : compare match 2 : underflow or overflow 3 : count direction change up/down count mode counts up on detecting speci- fied edge on the ain pin. counts down on detecting spec- ified edge on the bin pin. counter clear function gate function phase difference count mode (multiply by 2) reads the ain pin input level on detecting a rising or falling edge on the bin pin and counts up or counts down. counter clear function gate function phase difference count mode (multiply by 4) reads the ain pin input level on detecting a rising or falling edge on the bin pin and counts up or counts down. similarly, reads the bin pin input level on detect- ing a rising or falling edge on the ain pin and counts up or counts down. counter clear function gate function 16-bit 1-channel mode timer mode 2/ f , 4/ f ( f : machine clock frequency) ? up/down count mode counts up on detecting speci- fied edge on the ain pin. counts down on detecting spec- ified edge on the bin pin. counter clear function gate function phase difference count mode (multiply by 2) reads the ain pin input level on detecting a rising or falling edge on the bin pin and counts up or counts down. counter clear function gate function phase difference count mode (multiply by 4) reads the ain pin input level on detecting a rising or falling edge on the bin pin and counts up or counts down. similarly, reads the bin pin input level on detect- ing a rising or falling edge on the ain pin and counts up or counts down. counter clear function gate function
mb90520a/520b series 50 ? block diagram rcr0 udcr0 zin0 bin0 ain0 ctut ucre rlde udcc cgsc cge1 cge0 ? cite udie cmpf ovff udff udf1 udf0 cstr cdcf cfie clks cms1cms0 ces1 ces0 m16e internal data bus reload compare register 0 reload control circuit up/down count register 0 carry/ borrow (to channel 1) counter control register 0 (ccr0: l) pin pin pin edge/level detection circuit counter clear circuit overflow underflow compare control circuit machine clock pre- scaler up/down count selector count clock counter status register 0 (csr0) edge detection circuit interrupt request interrupt request counter control register 0 (ccr0: h) m16e (to channel 1) 8/16-bit up/down counter/timer 0
mb90520a/520b series 51 ? pins and interrupt numbers 8/16-bit up/down counter/timer 0 ain0 pin : p24/ain0 bin0 pin : p25/bin0 zin0 pin : p26/zin0 compare match interrupt number : #21 (15 h ) interrupt number for underflow/overflow interrupt, count direction change interrupt : #2 (16 h ) 8/16-bit up/down counter/timer 1 ain1 pin : p50/ain1 bin1 pin : p51/bin1 zin1 pin : p52/zin1 compare match interrupt number : #29 (1d h ) interrupt number for underflow/overflow interrupt, count direction change interrupt : #3 (1e h ) rcr1 udcr1 zin1 ain1 bin1 ctut ucre rlde udcc cgsc cge1 cge0 ? cite udie cmpf ovff udff udf1 udf0 cstr cdcf cfie clks cms1cms0 ces1 ces0 ? internal data bus reload compare register 1 reload control circuit up/down count register 1 counter control register 1 (ccr1: l) pin pin pin edge/level detection circuit counter clear circuit overflow underflow compare control circuit machine clock pre- scaler up/down count clock selector count clock counter status register 1 (csr1) edge detection circuit interrupt request interrupt request counter control register 1 (ccr1: h) carry/borrow (from channel 0) m16e (from channel 1) 8/16-bit up/down counter/timer 1
mb90520a/520b series 52 8. extended i/o serial interfaces 0 and 1 ? the extended i/o serial interfaces are serial i/o interfaces that perform clock-synchronized data transfer. ? the mb90520a/520b series contain two internal extended i/o serial interface channels. ? either lsb-first or msb-first data transmission format can be selected. ? extended i / o serial interface functions function transmission direction transmit and receive can be handled simultaneously. (a setting is required to select transmit or receive.) transmission mode clock synchronous (data transfer only) transmission clock internal shift clock mode (uses the communications prescaler output clock.) external shift clock mode (inputs the clock signal from sck1 and sck2.) transmission speed when using internal shift clock : up to 1 mhz operation can be achieved (for a 16 mhz machine clock with the divisor setting for the communication prescaler set to 8) . speeds faster than 1 mhz are not possible. when using an external shift clock : as a minimum of 5 machine cycles are required, when the machine clock is 16 mhz the maximum input frequency for the external shift clock is 16 mhz / 5 = 3.2 mhz. data transmission format lsb-first or msb-first, selectable data transfer only number of data bits = 8 (fixed) interrupt request generation interrupt generated when transfer completes ei 2 os support supports use of the extended intelligent i/o service.
mb90520a/520b series 53 ? block diagram ???? mode bds soe scoe smd2 smd1 smd0 sie sir busy stop strt ??? md div3 div2 div1 div0 sin sck sot internal data bus (msb-first) d7 to d0 d7 to d0 (lsb-first) transmission direction selection pin pin serial data register (sdr) read write pin control circuit shift clock counter machine clock communications prescaler serial mode control status register (smcs) interrupt request communications prescaler register (cdcr)
mb90520a/520b series 54 9. uart (sci : serial communication interface) ? the uart (sci) is a general-purpose serial communications interface for performing synchronous or asyn- chronous communications with external devices. ? the interface provides bi-directional communications in both clock synchronous and clock asynchronous modes. ? includes a master-slave communication function (multi-processor mode) . ? can generate interrupt requests at receive complete, receive error detected, and transmit complete timings. also supports ei 2 os. ? uart ( sci ) functions function data buffer full-duplex double-buffered transmission modes clock synchronous (with no start/stop bit, no parity bit) clock asynchronous (start-stop sync) baud rate can use dedicated baud rate generator. can use external clock input. can use clock supplied by 16-bit reload timer 0. for machine clock speeds of 6 mhz, 8 mhz, 10 mhz, 12 mhz, and 16 mhz : available speeds for asynchronous communications : 31250 bps, 9615 bps, 4808 bps, 2404 bps, and 1202 bps available speeds for synchronous communications : 1 mbps, 500 kbps, 250 kbps, 125 kbps, and 62.5 kbps number of data bits 7 bits (when parity is used for asynchronous normal mode) 8 bits (when parity is not used) signal format non return to zero (nrz) format receive error detection framing errors (not available in clock synchronous mode) overrun errors parity errors (not available in clock synchronous mode and multi-processor mode) interrupt requests receive interrupt (receive complete or receive error detected) transmit interrupt (transmission complete) both transmit and receive support the extended intelligent i/o service (ei 2 os) . master/slave communication function (multi-processor mode) used for 1 (master) to n (slave) communications. (can only be used as master) ei 2 os support supports the extended intelligent i/o service (ei 2 os)
mb90520a/520b series 55 ? uart ( sci ) operation modes : available : not available + 1 : address/data bit used for communication control notes : ? the number of data bits must be set to eight for multi-processor and clock synchronous modes. ? a parity bit cannot be used in multi-processor and clock synchronous modes. ? only data can be transferred in clock synchronous mode. start and stop bits cannot be added to the trans- mission data. operation mode no. of data bits parity bit no. of stop bits 7 bits 8 bits none use 1 bit 2 bits mode 0 asynchronous normal mode (1-to-1) mode 1 asynchronous multi-processor mode (1-to-n) ( + 1) mode 2 clock synchronous clock synchronous mode (one-to-one)
mb90520a/520b series 56 ? block diagram sck pin pin sin sot md1 md0 cs2 cs1 cs0 soe scke md div3 div2 div0 div1 pen p sbl cl a/d rec txe rxe pe ore fre rdrf tdre tie rie control bus dedicated baud rate generator 16-bit reload timer 0 clock selector receive clock transmit clock receive control circuit start bit detection circuit receive bit counter receive parity counter receive shift register serial input data register transmission control circuit transmission start circuit transmit bit counter transmit parity counter transmission shift register serial output data register receive complete receive status evaluation circuit receive interrupt request output transmit interrupt request output pin transmission start receive error detection signal for ei 2 os internal data bus communi- cation prescaler register serial mode register serial control register serial status register
mb90520a/520b series 57 10. dtp (data transfer peripheral) /external interrupt circuit the dtp/external interrupt function detects interrupt requests and data transfer requests input from external devices and passes these to the cpu as external interrupt requests. this block can also activate the extended intelligent i/o service (ei 2 os) . ? dtp / external interrupt functions external interrupt dtp function input pins 8 channels (int0 to int7) interrupt conditions can be set independently for each channel (each pin) in the detection level setup register (elvr) . h level, l level, rising edge, or falling edge input h level or l level input interrupt control interrupts can be enabled or disabled in the dtp/external interrupt enable register (enir) . interrupt flag the dtp/external interrupt request register (eirr) stores interrupt requests. processing selection set ei 2 os to be disabled (icr : ise = 0) set ei 2 os to be enabled (icr : ise = 1) interrupt execution jumps to interrupt handler routine jumps to interrupt handler routine after automatic data transfer by ei 2 os completes. ei 2 os support supports the extended intelligent i/o service (ei 2 os)
mb90520a/520b series 58 ? block diagram int7 int6 int5 int4 lb7 la7 lb6 la6 lb5 la5 lb4 la4 er7 er6 er5 er4 er3 er2 int3 int2 int1 int0 lb3 la3 lb2 la2 lb1 la1 lb0 la0 er1 er0 en7 en6 en5 en4 en3 en2 en1 en0 detection level setting register (elvr) pin pin pin pin pin pin pin pin level/edge selector level/edge selector level/edge selector level/edge selector level/edge selector level/edge selector level/edge selector level/edge selector internal data bus dtp/external interrupt input detection circuit dtp/external interrupt request register (eirr) dtp/external interrupt enable register (enir) interrupt request signal interrupt request signal
mb90520a/520b series 59 11. wakeup interrupts ? the wakeup interrupt function detects wakeup interrupt requests from external devices by detecting l levels input to the wakeup interrupt input pins (wi0 to wi7) and passes these to the cpu for interrupt processing. ? wakeup interrupts can be used to wakeup the microcontroller from standby mode. (however, wakeup interrupts cannot be used to recover from hardware standby mode.) ? not supported by the extended intelligent i/o service (ei 2 os) . ? wakeup interrupt functions ? block diagram function and control input pins 8 channels (8 pins : wi0 to wi7) interrupt trigger l level inputs. one interrupt flag is shared by all eight channels. interrupt control interrupt requests can be enabled or disabled in the wakeup interrupt control register (eicr) . interrupt flag interrupt requests are stored in the wakeup interrupt flag register (eifr) . ei 2 os support not supported by the extended intelligent i/o service (ei 2 os) . ??????? wif en7 en6 en5 en4 en3 en2 en1 en0 wi0 wi1 wi2 wi3 wi4 wi5 wi6 wi7 internal data bus wakeup interrupt control register (eicr) wakeup interrupt flag register (eifr) interrupt request detection circuit pin pin pin pin pin pin pin pin wakeup interrupt request ? : undefined
mb90520a/520b series 60 12. delayed interrupt generation module the delayed interrupt generation module is used to generate the task switching interrupt. generation of this hardware interrupt can be specified by software. ? delayed interrupt generation module functions ? block diagram function and control interrupt trigger writing 1 to bit r0 of the delayed interrupt request generation/clear register (dirr : r0 = 1) generates an interrupt request. writing 0 to bit r0 of the delayed interrupt request generation/clear register (dirr : r0 = 0) clears the interrupt request. interrupt control no enable/disable register is provided for this interrupt. interrupt flag set in bit r0 of the delayed interrupt request generation/clear register (dirr : r0) . ei 2 os support not supported by the extended intelligent i/o service (ei 2 os) . ??????? r0 internal data bus delayed interrupt request generation/clear register (dirr) interrupt request latch s r interrupt request signal ? : undefined
mb90520a/520b series 61 13. 8/10-bit a/d converter ? the 8/10-bit a/d converter uses rc successive approximation to convert analog input voltages to an 8-bit or 10-bit digital value. ? the input signals can be selected from the eight analog input pin channels. ? either a software trigger, internal timer output, or external pin trigger can be selected to trigger the start of a/ d conversion. ? 8 / 10 - bit a / d converter functions ? 8 / 10 - bit a / d converter conversion modes function a/d conversion time sampling time : can be selected from 64, 128, or 4096 machine cycles. the minimum is 4 m s. compare time : can be selected from 44, 99, or 176 machine cycles. the minimum is 4.4 m s. a/d conversion time = sampling time + conversion time. the minimum a/d conversion time is 10.2 m s. conversion method rc successive approximation with sample & hold circuit resolution 8-bit or 10-bit, selectable analog input pins up to eight channels can be used. however, two or more channels cannot be used simultaneously. interrupts an interrupt request can be generated when a/d conversion completes. a/d conversion start trigger selectable : software, internal timer output, or falling edge on input from external pin ei 2 os support supported by the extended intelligent i/o service (ei 2 os) . description single-shot conversion mode performs a/d conversion sequentially from the start channel to the end channel. a/d con- version halts after conversion completes for the end channel. continuous conversion mode performs a/d conversion sequentially from the start channel to the end channel. a/d con- version starts again from the start channel after conversion completes for the end channel. incremental conversion mode a/d conversion is performed for one channel then halts until the next trigger. after conver- sion is performed for the end channel, the next conversion is performed for the start chan- nel, and repeated this operation.
mb90520a/520b series 62 ? block diagram busy int inte paus sts1 sts0 stat re- served md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 an7 an6 adtg to an5 an4 an3 an2 an1 an0 avrh, avrl av cc av ss 2 6 2 2 2 f selb st1 st0 ct1 ct0 ? d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a/d control status register (adcs) interrupt request output trigger selector decoder internal data bus analog channel selector sample & hold circuit comparator control circuit d/a converter a/d data register (adcr) to : internal timer output ? : undefined reserved : always set to 0. f : machine clock
mb90520a/520b series 63 14. 8-bit d/a converter ? the 8-bit d/a converter performs r-2r d/a conversion with 8-bit resolution. ? two d/a converter channels with independent analog outputs are provided. ? d / a converter functions ? d / a converter theoretical output voltage note : dv cc voltage : d/a converter reference voltage. this must not exceed v cc . also, always ensure that dv ss is equipotential to v ss . function d/a conversion time the settling time is 12.5 m s. this is independent of the machine clock. conversion method r-2r conversion resolution 8-bit analog output pins two output pins are provided. both pins can be used simultaneously. interrupts none d/a conversion trigger set the digital value in the d/a data register (dadr) , then enable d/a output in the d/a control register (dacr) to start analog output from the d/a output pin. ei 2 os support not supported by the extended intelligent i/o service (ei 2 os) . d/a data register setting theoretical output voltage value 00 h 0 / 256 dv cc voltage ( = 0 v) 00 h 1 / 256 dv cc voltage fe h 254 / 256 dv cc voltage ff h 255 / 256 dv cc voltage
mb90520a/520b series 64 ? block diagram da7 da6 da5 da4 da3 da2 da1 da0 ??????? dae da7 da6 da5 da4 da3 da2 da1 da0 2r dvr dv ss da 2r 2r 2r 2r 2r 2r 2r r r r r r r r 2r internal data bus internal data bus d/a data register (dadr) d/a conversion circuit pin standby control (spl = 1) d/a control register (dacr) standby control : controls stop mode (spl = 1) , pseudo-clock mode (spl = 1) , clock mode (spl = 1) , and hardware standby mode.
mb90520a/520b series 65 15. clock timer ? the clock timer is a 15-bit freerun timer that counts up synchronized with the sub-clock. ? seven different interval time settings are available. ? this timer provides the clock for the sub-clocks oscillation stabilization delay timer and the watchdog timer. ? this timer always counts the sub-clock, regardless of the settings in the clock selection register (cksc) . ? clock timer functions ? clock timer interval times sclk : sub-clock frequency the values enclosed in ( ) are the times for a sub-clock frequency of 8.192 khz. note that the sub-oscillation clock is divided by four to generate the sub-clock frequency. the sub-oscillation clock operates at 32.768 khz. ? clock periods generated by clock timer sclk : sub-clock frequency the values enclosed in ( ) are the times for a sub-clock frequency of 8.192 khz. note that the sub-oscillation clock is divided by four to generate the sub-clock frequency. the sub-oscillation clock operates at 32.768 khz. function interval time selectable from the seven settings shown in the table below. clock timer size 15-bit clock supply oscillation stabilization delay timer for sub-clock and watchdog timer source clock sub-oscillation clock divided by four. (sclk : sub-clock) interrupts interval time overflow ei 2 os support not supported by the extended intelligent i/o service (ei 2 os) . sub-clock period interval time sclk (122 m s) 2 9 /sclk (approx. 62.5 ms) 2 10 /sclk (approx. 125.0 ms) 2 11 /sclk (approx. 250.0 ms) 2 12 /sclk (approx. 500.0 ms) 2 13 /sclk (approx. 1.0 s) 2 14 /sclk (approx. 2.0 s) 2 16 /sclk (approx. 4.0 s) clock supply clock period oscillation stabilization delay timer for sub-clock 2 14 /sclk (approx. 2.0 s) watchdog timer 2 10 /sclk (approx. 125.0 ms) 2 13 /sclk (approx. 1.0 s) 2 14 /sclk (approx. 2.0 s) 2 16 /sclk (approx. 4.0 s)
mb90520a/520b series 66 ? block diagram of : overflow sclk : sub-clock frequency wdcs sce wtie wtof wtr wtc2 wtc1 wtc0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 15 2 14 of of of of of of of sclk clock timer counter to watchdog timer power-on reset change to hardware standby mode change to stop mode counter clear circuit interval timer selector to oscillation stabilization delay timer for sub-clock clock timer interrupt clock timer control register (wtc)
mb90520a/520b series 67 16. lcd controller/driver ? the lcd controller/driver can drive an lcd (liquid crystal display) directly. ? the lcd is driven by 4 common outputs and 32 segment outputs. ? the output mode can be set to 1/2, 1/3, or 1/4 duty. ? lcd controller / driver functions ? bias , duty , and common output combinations function divider resistor for lcd drive power either the internal resistor (approx. 100 k w ) or an externally connected resistor can be selected. common outputs max 4 outputs (the corresponding pins cannot be used as i/o ports when using an lcd.) segment outputs max 32 outputs (of these, 24 pins can be used as i/o ports in blocks of 8 pins.) display data memory 16 bytes of ram for internal display are provided duty 1/2, 1/3, or 1/4 can be selected. bias 1/3 only supported drive clock either the oscillation clock (hclk) or sub-clock (sclk) can be used. interrupts none ei 2 os support not supported by the extended intelligent i/o service (ei 2 os) . bias 1/2 duty output mode 1/3 duty output mode 1/4 duty output mode 1/3 bias com0 and com1 outputs used com0 to com2 outputs used com0 to com3 outputs used
mb90520a/520b series 68 ? block diagram 6 32 2 2 4 hclk sclk css lcen vsel bk ms1 v0 v1 v2 v3 com0 com1 com2 com3 seg0 seg1 seg2 seg29 seg30 seg31 ms0 fp1 fp0 com3 com2 com1 com0 ???? seg5 re- served re- served seg4 seg3 seg2 seg1 seg0 common pin selection register (lcdcmr) lcdc control register 0 (lcr0) internal data bus prescaler timing controller display data memory (16 bytes) lcdc control register 1 (lcr1) controller pin pin pin pin pin pin pin pin pin pin pin pin pin pin internal divider resistor common driver segment driver ac conversion circuit driver ? : undefined bit hclk : main clock sclk : sub-clock
mb90520a/520b series 69 17. communications prescaler ? supplies the clock to the dedicated baud rate generator used by the uart (sci) and extended i/o serial interfaces. ? by dividing the machine clock to produce the clock supply to the dedicated baud rate generator, the baud rate can be specified independently of the machine clock speed. ? the communications prescaler can divide the machine clock frequency f by the following seven ratios to generate the clock supply to the dedicated baud rate generator and extended i/o serial interface : f /2, f /3, f /4, f /5, f /6, f /7, f /8 ? communications prescaler functions note : as the same output from the communications prescaler is supplied to both the uart (sci) and the extended i/o serial interface, the transfer clock speed settings must be revised if the communications prescaler settings are changed. ? block diagram function clock supply dedicated baud rate generator for the uart (sci) and the extended i/o serial interface. however, the same clock is supplied to both peripherals. divided clock frequency f /2, f /3, f /4, f /5, f /6, f /7, f /8 ( f : machine clock frequency) interrupts none ei 2 os support not supported by the extended intelligent i/o service (ei 2 os) . ? md ?? div3 div2 div1 div0 f /2 f /3 f /4 f /5 f /6 f /7 f /8 f smcs:smd2 ~ smd0 = 000 b ~ 100 b smr:cs2 ~ cs0 = 000 b ~ 100 b uart cdcr extended serial i/o communications prescaler ? : undefined f : machine clock frequency
mb90520a/520b series 70 18. address match detection function ? if the program address during program execution matches the value set in one of the detection address setting registers (padr) , the address match detection function replaces the instruction being executed with the int9 instruction and executes the interrupt handler program. ? the address match detection function provides a simple method of correcting programming errors (patching) using ram or similar. ? address match detection functions ? block diagram function no. of address settings two channels (two addresses can be set) interrupts an interrupt is generated when the program address matches the detection address setting register. ei 2 os support not supported by the extended intelligent i/o service (ei 2 os) . ade1 reserved reserved reserved reserved add1 ade0 add0 padr1 (24 bit) padr0 (24 bit) address latch pacsr internal data bus detection address setting register detection address setting register address detection control register (pacsr) comparator int9 instruction (generates an int9 interrupt) reserved : always set to 0.
mb90520a/520b series 71 19. rom mirror function selection module the rom mirror function selection module enables rom data in ff bank to be read by accessing 00 bank. ? rom mirror function selection module functions ? relationship between addresses in the rom mirror function ? block diagram function mirror setting address data in ffffff h to ff4000 h in ff bank can be read from 00ffff h to 004000 h in 00 bank. interrupts none ei 2 os support not supported by the extended intelligent i/o service (ei 2 os) . 004000 h 00ffff h fe0000 h feffff h ff0000 h ff4000 h ffffff h 00 bank mirror area mirrored rom data area in ff bank rom area in mb90523a, 523b, and f523b rom area in mb90522a and 522b ??????? mi rom rom mirror function selection register (romm) internal data bus address data address space ff bank 00 bank
mb90520a/520b series 72 20. low power consumption (standby) modes the power consumption of f 2 mc-16lx devices can be reduced by various settings relating to the operating clock selection. ? functions of each cpu operation mode cpu operation clock operation mode explanation pll clock normal run the cpu and peripheral functions operate using the oscillation clock (hclk) mul- tiplied by the pll circuit. sleep the peripheral functions only operate using the oscillation clock (hclk) multiplied by the pll circuit. pseudo- clock the timebase timer only operates using the oscillation clock (hclk) multiplied by the pll circuit. stop the oscillation clock is stopped and the cpu and peripherals halt operation. main clock normal run the cpu and peripheral functions operate using the oscillation clock (hclk) di- vided by 2. sleep the peripheral functions only operate using the oscillation clock (hclk) divided by 2. stop the oscillation clock is stopped and the cpu and peripherals halt operation. sub-clock normal run the cpu and peripheral functions operate using the sub-clock (sclk) . the os- cillation clock stops. sleep the peripheral functions only operate using the sub-clock (sclk) . the oscillation clock stops. clock the clock timer only operates using the sub-clock (sclk) . the oscillation clock stops. stop the oscillation clock and sub-clock are stopped and the cpu and peripherals halt operation. cpu intermittent operation normal run the oscillation clock (hclk) divided by 2 operates intermittently for fixed time in- tervals. hardware standby stop the oscillation clock and sub-clock are stopped and the cpu and peripherals halt operation.
mb90520a/520b series 73 21. clock monitor function the clock monitor function outputs the machine clock divided by a specified amount to the clock monitor pin (ckot) . ? clock monitor functions ? output frequency of the clock monitor function ? block diagram function output frequency machine clock divided by 2 to 32 (8 settings available) interrupts none ei 2 os support not supported by the extended intelligent i/o service (ei 2 os) . frq2 - 0 bits machine clock divide ratio when f f f f = = = = 16 mhz when f f f f = = = = 8 mhz when f f f f = = = = 4 mhz period frequency period frequency period frequency 000 b f /2 1 125 ns 8 mhz 250 ns 4 mhz 500 ns 2 mhz 001 b f /2 2 250 ns 4 mhz 500 ns 2 mhz 1.0 m s1 mhz 010 b f /2 3 500 ns 2 mhz 1.0 m s1 mhz2.0 m s 500 khz 011 b f /2 4 1.0 m s1 mhz2.0 m s500 khz4.0 m s 250 khz 100 b f /2 5 2.0 m s 500 khz 4.0 m s250 khz8.0 m s 125 khz 101 b f /2 6 4.0 m s 250 khz 8.0 m s 125 khz 16.0 m s62.5 khz 110 b f /2 7 8.0 m s 125 khz 16.0 m s 62.5 khz 32.0 m s 31.25 khz 111 b f /2 8 16.0 m s 62.5 khz 32.0 m s31.25 khz64.0 m s 15.625 khz cken frq2 ckot pin frq1 frq0 ???? 3 f internal data bus prescaler count clock selector output enable clock output enable register (clkr) ? : undefined f : machine clock frequency
mb90520a/520b series 74 22. 1 mbit flash memory ? this section describes the flash memory on the mb90f523b and does not apply to evaluation products and mask rom versions. ? the flash memory is located in banks fe to ff in the cpu memory map. ? flash memory functions * : embedded algorithm is a trademark of advanced micro devices. ? sector configuration of flash memory function memory size 1 mbit (128 kbytes) memory configuration 128 kwords 8 bits or 64 kwords 16 bits sector configuration 16 kbytes + 8 kbytes + 8 kbytes + 32 kbytes + 64 kbytes sector protect function selectable for each sector programming algorithm automatic programming algorithm (embedded algorithm * : equivalent to mbm29f400ta) operation commands compatible with jedec standard commands includes an erase pause and restart function data polling and toggle bit write/erase completion erasing by sector available (sectors can be combined in any combination) no. of write/erase cycles min 10,000 guaranteed memory write/erase method can be written and erased using a parallel writer (minato electronics model 1890a, ando denki af9704, af9705, af9706, af9708, and af9709) can be written and erased using a dedicated serial writer (ydc af200, af210, af120, and af110) can be written and erased by the program interrupts write and erase completion interrupts ei 2 os support not supported by the extended intelligent i/o service (ei 2 os) . sa0 (64 kbyte) sa1 (32 kbyte) sa2 (8 kbyte) sa3 (8 kbyte) sa4 (16 kbyte) fe0000 h fefff h ff0000 h ff7fff h ff8000 h ff9fff h ffa000 h ffbfff h ffc000 h feffff h 60000 h 6ffff h 70000 h 77fff h 78000 h 79fff h 7a000 h 7bfff h 7c000 h 7ffff h flash memory cpu address writer address* * : the writer address is the address to use instead of the cpu address when writing data from a parallel flash memory writer. use the writer address when programming or erasing using a general-purpose parallel writer.
mb90520a/520b series 75 ? pins used for fujitsu standard serial on - board programming ? overall configuration of connection between serial writer and mb90f523a fujitsu standard serial on-board programming uses a flash microcontroller writer made by ydc. note : contact ydc for details of the functions and operation of the flash microcontroller writer (af220, af210, af120, or af110) , standard connection cable (az210) , and connectors. pin function explanation md2, md1, md0 mode pins setting md2 = md1 = 1, md0 = 0 selects flash memory serial program- ming mode. x0, x1 oscillation input pin flash memory serial programming mode uses the pll clock with the multiplier set to 1 as the machine clock. set the oscillation frequency used for serial programming to between 3 mhz and 16 mhz. p00, p01 write program activation pins input p00 = 0 (l level) and p01 = 1 (h level) rst reset pin ? hst hardware standby pin input an h level during flash memory serial programming mode. sin0 serial data input pin uses the uart (sci) in clock synchronous mode. sot0 serial data output pin sck0 serial clock input pin cc pin capacitor pin for power supply stabilization. connect an external capac- itor of approx. 0.1 m f. v cc power supply voltage pins if the user system can provide the programming voltage (5 v 10 % ) , do not need to connect to the flash microcontroller writer. v ss gnd pin connect to common gnd with the flash microcontroller writer. host interface cable (az221) standard cable (az210) flash microcontroller writer + memory card clock synchronous serial mb90f523a/b user system can operate standalone rs232c
mb90520a/520b series 76 n electrical characteristics\ 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1 : av cc , avrh, avrl, and dv cc shall never exceed v cc . avrh and avrl shall never exceed av cc . also, avrl shall never exceed avrh. *2 : v cc 3 av cc 3 dv cc 3 3.0 v. *3 : v i and v o shall never exceed v cc + 0.3 v. *4 : the maximum output current is the peak value for a single pin. *5 : the average output current is the average current value for a single pin during a 100 ms period. *6 : the total average current is the average current for all pins during a 100 ms period. note : average output current = operating current operating ratio warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v * 1 avrh, avrl v ss - 0.3 v ss + 6.0 v * 1 dv cc v ss - 0.3 v ss + 6.0 v * 2 input voltage v i v ss - 0.3 v ss + 6.0 v * 3 output voltage v o v ss - 0.3 v ss + 6.0 v * 3 l level maximum output current i ol ? 15 ma * 4 l level average output current i olav ? 4ma* 5 l level total maximum output current s i ol ? 100 ma l level total average output current s i olav ? 50 ma * 6 h level maximum output current i oh ?- 15 ma * 4 h level average output current i ohav ?- 4ma* 5 h level total maximum output current s i oh ?- 100 ma h level total average output current s i ohav ?- 50 ma * 6 power consumption pd ? 400 mw mb90522a/523a/ f523b ? 300 mw mb90522b/523b operating temperature ta - 40 + 85 c storage temperature tstg - 55 + 150 c
mb90520a/520b series 77 2. recommended operating conditions (v ss = av ss = 0.0 v) note : use a ceramic capacitor or other capacitor with equivalent frequency characteristics. the capacitance of the smoothing capacitor connected to the v cc pin must be greater than c s . warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage v cc 3.0 5.5 v smoothing capacitor c s 0.1 1.0 m f operating temperature ta - 40 + 85 c c c s c pin diagram
mb90520a/520b series 78 3. dc characteristics (av cc = v cc = 5.0 v 10 % , av ss = v ss = dv ss = 0.0 v, ta = - 40 c to + 85 c) (continued) parameter sym- bol pin name condition value unit remarks min typ max h level input voltage v ihs p20 to p27, p30 to p37, p53, p54, p70 to p77, p80 to p87, pa0 to pa7 v cc = 3.0 v to 5.5 v 0.8 v cc ? v cc + 0.3 v v ihm md0 to md2 v cc - 0.3 ? v cc + 0.3 v l level input voltage v ils p20 to p27, p30 to p37, p53, p54, p70 to p77, p80 to p87, pa0 to pa7 v ss - 0.3 ? 0.2 v cc v v ilm md0 to md2 v ss - 0.3 ? v ss + 0.3 v h level output voltage v oh all output pins other than p90 to p97 v cc = 4.5 v i oh = - 2.0 ma v cc - 0.5 ?? v l level output voltage v ol all output pins v cc = 4.5 v i ol = 2.0 ma ?? 0.4 v input leak current i il all output pins other than p90 to p97 v cc = 5.5 v v ss < v i < v cc - 5 ? 5 m a open-drain output leak current i leak p90 to p97 output pins ?? 0.1 5 m a pull-up resistor r up p00 to p07, p10 to p17 p40 to p47, md0, md1 ? 50 100 200 k w pull-down resistor r down md2 50 100 200 k w power supply current * i cc v cc for v cc = 5 v, internal frequency = 16 mhz, normal operation ? 40 65 ma mb90522a/ 523a ? 30 60 ma mb90f523b ? 30 40 ma mb90522b/ 523b
mb90520a/520b series 79 (av cc = v cc = 5.0 v 10 % , av ss = v ss = dv ss = 0.0 v, ta = - 40 c to + 85 c) (continued) parameter sym- bol pin name condition value unit remarks min typ max power supply current * i cc v cc for v cc = 5 v, internal frequency = 8 mhz, normal operation ? 20 25 ma mb90522a/ 523a ? 15 20 ma mb90f523b ? 15 20 ma mb90522b/ 523b for v cc = 5 v, internal frequency = 16 mhz, a/d operation in progress ? 50 70 ma mb90522a/ 523a ? 45 65 ma mb90f523b ? 35 45 ma mb90522b/ 523b for v cc = 5 v, internal frequency = 8 mhz, a/d operation in progress ? 25 30 ma mb90522a/ 523a ? 20 25 ma mb90f523b ? 20 25 ma mb90522b/ 523b for v cc = 5 v, internal frequency = 16 mhz, d/a operation in progress ? 55 70 ma mb90522a/ 523a ? 50 70 ma mb90f523b ? 40 50 ma mb90522b/ 523b for v cc = 5 v, internal frequency = 8 mhz, d/a operation in progress ? 30 35 ma mb90522a/ 523a ? 25 30 ma mb90f523b ? 20 25 ma mb90522b/ 523b writing or erasing flash memory ? 50 75 ma mb90f523b i ccs for v cc = 5 v, internal frequency = 16 mhz, sleep mode ? 815ma mb90522a/ 523a ? 15 20 ma mb90f523b /522b/523b for v cc = 5 v, internal frequency = 8 mhz, sleep mode ? 710ma mb90522a/ 523a ? 12 18 ma mb90f523b /522b/523b i ccl for v cc = 5 v, internal frequency = 8 khz, sub-clock mode, ta = 25 c ? 0.1 1.0 ma mb90522a/ 523a/522b/ 523b ? 4 7 ma mb90f523b
mb90520a/520b series 80 (continued) (av cc = v cc = 5.0 v 10 % , av ss = v ss = dv ss = 0.0 v, ta = - 40 c to + 85 c) * : current values are provisional and are subject to change without notice to allow for improvements to the char- acteristics. the power supply current is measured with an external clock. parameter sym- bol pin name condition value unit remarks min typ max power supply current * i ccls v cc for v cc = 5 v, internal frequency = 8 khz, sub-sleep mode, ta = 25 c ? 30 50 m a i cct for v cc = 5 v, internal frequency = 8 khz, clock mode, ta = 25 c ? 15 30 m a i cch sleep mode, ta = 25 c ? 520 m a input capacitance c in other than av cc , av ss , c, v cc , and v ss ?? 10 80 pf lcd divider resistor r lcd v0 - v1, v1 - v2, v2 - v3 ? 50 100 200 k w output impedance for com0 to com3 r vcom com0 to com3 v1 to v3 = 5.0 v ?? 2.5 k w output impedance for seg00 to seg31 r vseg seg00 to seg31 ?? 15 k w lcdc leak current i lcdc v0 to v3, com0 to com3, seg00 to seg31 ??? 5 m a
mb90520a/520b series 81 4. ac characteristics (1) reset and hardware standby input timings (av cc = v cc = 5.0 v 10 % , av ss = v ss = dv ss = 0.0 v, ta = - 40 c to + 85 c) * : see (3) clock timings for more information about t cp (internal operating clock cycle time) . parameter symbol pin name condition value unit remarks min typ reset input time t rstl rst ? 4 t cp * ? ns hardware standby input time t hstl hst 4 t cp * ? ns rst hst 0.2 v cc t rstl , t hstl 0.2 v cc c l pin c l is the load capacitance for the pin during testing. measurement conditions for ac ratings
mb90520a/520b series 82 (2) power-on reset (av cc = v cc = 5.0 v 10 % , av ss = v ss = dv ss = 0.0 v, ta = - 40 c to + 85 c) * : v cc must be less than 0.2 v before power-on. notes : the above rating values are for generating a power-on reset. when hst = l, always apply the power supply in accordance with the above ratings regardless of whether a power-on reset is required. some internal registers are only initialized by a power-on reset. always apply the power supply in cordance with the above ratings if you wish to initialize these registers. parameter symbol pin name condi- tion value unit remarks min typ power supply rise time t r v cc ? 0.05 30 ms * power supply cutoff time t off v cc 4 ? ms for repeated operation v cc v cc 3.0 v v ss t r 0.2 v 0.2 v 2.7 v t off 0.2 v maintain ram data recommended rate of voltage rise is 50 mv/ms or less. sudden changes in the power supply voltage may cause a power-on reset. the recommended practice if you wish to change the power supply voltage while the device is operating is to raise the voltage smoothly as shown below. also, changes to the supply voltage should be performed when the pll clock is not in use. the pll clock may be used, however, if the rate of voltage change is 1 v/s or less.
mb90520a/520b series 83 (3) clock timings (av cc = v cc = 5.0 v 10 % , av ss = v ss = dv ss = 0.0 v, ta = - 40 c to + 85 c) parameter sym- bol pin name condi- tion value unit remarks min typ max clock frequency f c x0, x1 ? 3 ? 16 mhz f cl x0a, x1a ?? 32.768 ? khz clock cycle time t hcyl x0, x1 ? 62.5 ? 333 ns t lcyl x0a, x1a ?? 30.5 ?m s input clock pulse width p wh p wl x0 ? 10 ?? ns recommended duty ratio = 30 % to 70 % p wlh p wll x0a ? 15.2 ?m s input clock rise/fall time t cr t cf x0 ??? 5ns when using an external clock internal operating clock frequency f cp ?? 1.5 ? 16 mhz when using main clock f lcp ??? 8.192 ? khz when using sub-clock internal operating clock cycle time t cp ?? 62.5 ? 666 ns when using main clock t lcp ??? 122.1 ?m s when using sub-clock 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc x0 t hcyl p wh p wl t cf t cr x0 and x1 clock timing 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc x0a t lcyl p wlh p wll t cf t cr x0a and x1a clock timing
mb90520a/520b series 84 the ac ratings are measured at the following reference voltages. 5.5 4.5 3.0 2.7 16 12 8 9 4 6 3 2 3468 source oscillation clock f cp (mhz) 12 16 1.5 3 8 internal clock f cp (mhz) 10 16 supply voltage v cc (v) guaranteed operation range for mb90v520a pll guaranteed operation range a/d, d/a guaranteed voltage range guaranteed operation range for mb90522a, 523a, mb90522b, 523b, and f523b 4 3 2 1 divided by 2 internal clock f cp (mhz) relationship between internal operating clock frequency and power supply voltage relationship between oscillation frequency and internal operating clock frequency pll guaranteed operation range 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc input signal waveform hysteresis input pin pins other than hysteresis input or md input pins output signal waveform output pin
mb90520a/520b series 85 (4) clock output timings (av cc = v cc = 5.0 v 10 % , av ss = v ss = dv ss = 0.0 v, ta = - 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ cycle time t cyc clk v cc = 5.0 v 10 % 62.5 ? ns clk - ? clk t chcl 20 ? ns clk t cyc 2.4 v 2.4 v 0.8 v t chcl
mb90520a/520b series 86 (5) uart (sci) timings (av cc = v cc = 5.0 v 10 % , av ss = v ss = dv ss = 0.0 v, ta = - 40 c to + 85 c) * : see (3) clock timings for more information about t cp (internal operating clock cycle time) . notes : these are the ac ratings for clk synchronous mode. c l is the load capacitor connected to the pin for testing. parameter sym- bol pin name condition value unit re- marks min typ serial clock cycle time t scyc sck0 to sck2 internal shift clock mode, output pin load is c l = 80 pf + 1 ttl 8 t cp * ? ns sck ? sot delay time t slov sck0 to sck2 sot0 to sot2 - 80 80 ns valid sin ? sck - t ivsh sck0 to sck2 sin0 to sin2 100 ? ns sck - ? valid sin hold time t shix sck0 to sck2 sin0 to sin2 60 ? ns serial clock h pulse width t shsl sck0 to sck2 external shift clock mode, output pin load is c l = 80 pf + 1 ttl 4 t cp * ? ns serial clock l pulse width t slsh sck0 to sck2 4 t cp * ? ns sck ? sot delay time t slov sck0 to sck2 sot0 to sot2 ? 150 ns valid sin ? sck - t ivsh sck0 to sck2 sin0 to sin2 60 ? ns sck - ? valid sin hold time t shix sck0 to sck2 sin0 to sin2 60 ? ns
mb90520a/520b series 87 sck0 to sck2 sot0 to sot2 sin0 to sin2 sck0 to sck2 sot0 to sot2 sin0 to sin2 t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc internal shift clock mode external shift clock mode
mb90520a/520b series 88 (6) timer input timings (av cc = v cc = 5.0 v 10 % , av ss = v ss = dv ss = 0.0 v, ta = - 40 c to + 85 c) * : see (3) clock timings for more information about t cp (internal operating clock cycle time) . (7) timer output timings (av cc = v cc = 5.0 v 10 % , av ss = v ss = dv ss = 0.0 v, ta = - 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ input pulse width t tiwh t tiwl ic00/01, ic10/11 ti0, ti1 ? 4 t cp * ? ns parameter symbol pin name condition value unit remarks min typ clk - ? t out change time t to out0 to out7 pg00/01 pg10/11 to0, to1 ? 30 ? ns ic00/01 ic10/11 ti0, ti1 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl clk (t out : out0 to out7, pg00/01, pg10/11, to0, to1) 2.4 v t to 2.4 v 0.8 v t out
mb90520a/520b series 89 5. electrical characteristics for the a/d converter (av cc = v cc = 5.0 v 10 % , av ss = v ss = dv ss = 0.0 v, 3.0 v avrh - avrl, ta = - 40 c to + 85 c) * : current when 8/10-bit a/d converter not used and cpu in stop mode (v cc = av cc = avrh = 5.0 v) note : see (3) clock timings in 4. ac ratings for more information about t cp (internal operating clock cycle time) . parameter sym- bol pin name value unit remarks min typ max resolution ?? ? 8/10 ? bit total error ?? ? ? 5.0 lsb linearity error ?? ? ? 2.5 lsb differential linearity error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an7 av ss - 3.5 lsb av ss + 0.5 lsb av ss + 4.5 lsb mv full-scale transition voltage v fst an0 to an7 avrh - 6.5 lsb avrh - 1.5 lsb avrh + 1.5 lsb mv a/d conversion time ?? 163 tcp ?? ns at machine clock = 16 mhz compare time ?? 99 tcp ?? ns at machine clock = 16 mhz analog port input current i ain an0 to an7 ?? 10 m a analog input voltage v ain an0 to an7 avrl ? avrh v reference voltage ? avrh avrl + 3.0 ? av cc v ? avrl 0 ? avrh - 3.0 v power supply current i a av cc ? 5 ? ma i ah av cc ?? 5 m a* reference voltage supply current i r avrh ? 400 ?m a i rh avrh ?? 5 m a* variation between channels ? an0 to an7 ?? 4lsb
mb90520a/520b series 90 6. a/d converter glossary (continued) resolution : the change in analog voltage that can be recognized by the a/d converter. linearity error : the deviation between the actual conversion characteristics and the line linking the zero transition point (00 0000 0000 b ?? 00 0000 0001 b ) and the full scale transi- tion point (11 1111 1110 b ?? 11 1111 1111 b ) . differential linearity error : the variation from the ideal input voltage required to change the output code by 1 lsb. total error : the total error is the difference between the actual value and the theoretical value. this includes the zero-transition error, full-scale transition error, and linearity error. 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h avrl digital output avrh 0.5 lsb 0.5 lsb v nt (measured value) {1 lsb (n - 1) + 0.5 lsb} total error analog input actual conversion characteristic actual conversion characteristic theoretical characteristic 1 lsb = (theoretical value) v ot (theoretical value) = avrl + 0.5 lsb [v] v nt : voltage at which digital output changes from (n - 1) to n avrh - avrl 1024 * [v] total error for digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb [lsb] v fst (theoretical value) = avrh - 1.5 lsb [v] * : for 10-bit resolution, this value is 1024 (2 10 ) . for 8-bit resolution, this value is 256 (2 8 ) .
mb90520a/520b series 91 (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h avrl avrh avrl avrh n + 1 n n - 1 n - 2 v nt v nt v (n + 1)t v ot (measured value) v fst {1 lsb (n - 1) + v ot } digital output linearity error analog input digital output differential linearity error analog input actual conversion characteristic actual conversion characteristic actual conversion characteristic actual conversion characteristic theoretical characteristic theoretical characteristic (measured value) (measured value) (measured value) (measured value) v ot : voltage at which digital output changes from 000 h to 001 h v fst : voltage at which digital output changes from 3fe h to 3ff h differential linearity error for digital output n = linearity error for digital output n = v ( n + 1 ) t - v nt 1 lsb - 1 lsb [lsb] v nt - {1 lsb (n - 1) + v ot } 1 lsb [lsb] 1 lsb = v fst - v ot 1022 * [v] * : for 10-bit resolution, this value is 1022 (2 10 - 2) . for 8-bit resolution, this value is 254 (2 8 - 2) .
mb90520a/520b series 92 7. notes for a/d conversion the recommended external circuit impedance of analog inputs for mb90v520 is approximately 5 k w or less, that for mb90f523b is approximately 15.5 k w or less, and that for mb90522a/523a/522b/523b is approximately 10 k w or less. if using an external capacitor, the capacitance should be several thousand times the level of the chips internal capacitor to allow for the partial potential between the external and internal capacitance. if the impedance of the external circuit is too high, the analog voltage sampling interval may be too short. (for sampling time = 4 m s, machine clock frequency = 16 mhz) . ?error the relative error increases as |avrh - avrl| becomes smaller. c r on analog input comparator mb90522a/523a/522b/523b r on = 2.2 k w approx. c = 45 pf approx. mb90f523b r on = 2.6 k w approx. c = 28 pf approx. note : the values listed are an indication only. ? block diagram of analog input circuit model
mb90520a/520b series 93 8. electrical characteristics for the d/a converter (av cc = v cc = 5.0 v 10 % , av ss = v ss = dv ss = 0.0 v, ta = - 40 c to + 85 c) 9. flash memory program/erase parameter symbol pin name value unit remarks min typ max resolution ?? ? 8 ? bit differential linearity error ?? ? ? 0.9 lsb absolute accuracy ?? ? ? 1.2 % linearity error ?? ? ? 1.5 lsb conversion time ?? ? 10 20 m s for load capacitance = 20 pf analog reference voltage ? dv cc v ss + 3.0 ? av cc v current consumption for reference voltage i dvr dv cc ? 120 300 m a i dvrs ?? 10 m a stop mode analog output impedance ?? ? 20 ? k w parameter condition value unit remarks min typ max sector erase time ta = + 25 c v cc = 5.0 v ? 115s excludes 00h programming prior erasure chip erase time ? 5 ? s excludes 00h programming prior erasure word (16-bit width) programming time ? 16 3,600 m s excludes system-level overhead program/erase cycle ? 10,000 ?? cycle data hold time ? 100 k ?? h
mb90520a/520b series 94 n example characteristics power supply current (mb90523a) (continued) i cc - v cc ta = + 25 c, external clock input i ccs - v cc ta = + 25 c, external clock input i ccl - v cc ta = + 25 c, external clock input i ccls - v cc ta = + 25 c, external clock input v cc (v) i cc (ma) 60 50 40 30 20 10 0 23 4 5 6 f = 16 mhz f = 12 mhz f = 10 mhz f = 8 mhz f = 4 mhz f = 2 mhz v cc (v) i ccs (ma) 20 15 10 5 0 23456 f = 2 mhz f = 4 mhz f = 8 mhz f = 10 mhz f = 12 mhz f = 16 mhz v cc (v) i ccl ( m a) 70 60 50 40 30 20 10 0 23 4 56 f = 8 khz v cc (v) i ccls ( m a) 20 15 10 5 0 23456 f = 8 khz
mb90520a/520b series 95 (continued) i cct - v cc ta = + 25 c, external clock input example mb90523a v oh - i oh characteristics ta = + 25 c, v cc = 4.5 v example mb90523a v ol - i ol characteristics ta = + 25 c, v cc = 4.5 v v cc (v) i cct ( m a) 234 5 6 f = 8 khz 0 2 4 6 8 10 i oh (ma) v cc - v oh (mv) 1000 900 800 700 600 500 400 300 200 100 0 2 1 0 3 4 5 6 7 8 9 10 11 12 i ol (ma) v ol (mv) 1000 900 800 700 600 500 400 300 200 100 0 2 1 0 3 4 5 6 7 8 9 10 11 12
mb90520a/520b series 96 n ordering information part no. package remarks mb90522apff mb90523apff MB90522BPFF mb90f523bpff 120-pin, plastic lqfp (fpt-120p-m05) mb90522apfv mb90523apfv mb90522bpfv mb90f523bpfv 120-pin, plastic qfp (fpt-120p-m13)
mb90520a/520b series 97 n package dimensions (continued) 120-pin plastic lqfp (fpt-120p-m05) * : pins width and pins thickness include plating thickness. dimensions in mm (inches) c 1998 fujitsu limited f120006s-3c-4 0.07(.003) m index 16.00?.20(.630?008)sq 14.00?.10(.551?004)sq 130 31 60 91 120 61 90 lead no. (stand off) 0.10?.10 (.004?004) 0.25(.010) (.018/.030) 0.45/0.75 (.020?008) 0.50?.20 (mounting height) 0~8 details of "a" part 1.50 +0.20 ?.10 +.008 ?004 .059 "a" 0.40(.016) 0.16?.03 (.006?001) 0.145?.055 (.006?002) 0.08(.003)
mb90520a/520b series 98 (continued) 120-pin plastic qfp (fpt-120p-m13) * : pins width and pins thickness include plating thickness. dimensions in mm (inches) c 2000 fujitsu limited f120013s-c-3-5 0?8 .139 ?008 +.013 ?.20 +0.32 3.53 .008 ?006 +.004 ?.15 +0.10 0.20 (stand off) 0.25(.010) details of "a" part 61 90 60 31 30 1 lead no. 91 120 20.00?.10(.787?004)sq 22.60?.20(.890?008)sq 0.50(.020) 0.22?.05 (.009?002) 0.08(.003) m "a" 0.08(.003) (.006?002) 0.145?.055 index 0.50?.20 (.020?008) 0.60?.15 (.024?006) (mouting height)
mb90520a/520b series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f 0203 ? fujitsu limited printed in japan

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